/*PSB4610 PITA-2 bridge control registers*/
#define PITA2_ICR 0x00 /* Interrupt Control Register */
-#define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
-#define PITA2_ICR_INT0_En 0x00020000 /* [RW] Enable INT0 */
+#define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
+#define PITA2_ICR_GP0_INT 0x00000004 /* [RC] GP0 Interrupt */
+ /* GP0_Int_En=1, GP0_Out_En=0 and low detected */
+#define PITA2_ICR_GP1_INT 0x00000008 /* [RC] GP1 Interrupt */
+#define PITA2_ICR_GP2_INT 0x00000010 /* [RC] GP2 Interrupt */
+#define PITA2_ICR_GP3_INT 0x00000020 /* [RC] GP2 Interrupt */
+#define PITA2_ICR_INT0_En 0x00020000 /* [RW] Enable INT0 */
#define PITA2_MISC 0x1C /* Miscellaneous Register */
#define PITA2_MISC_CONFIG 0x04000000
chip=candev->chip[i];
if(!chip || !(chip->flags&CHIP_CONFIGURED))
continue;
- sja1000p_irq_handler(irq, dev_id, regs);
+ sja1000p_irq_handler(irq, chip, regs);
}
icr=readl(candev->dev_base_addr + PITA2_ICR);
} while(icr & PITA2_ICR_INT0);
CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
- if((l!=0x55aa01cb)||(i!=0x11)) {
+ if(l!=0x55aa01cb) {
CANMSG("EMS CPC-PCI unexpected check values\n");
}