Use mdelay instead of udelay for long times.

[lincan.git] / lincan / src / pc_i03.c

diff --git a/lincan/src/pc_i03.c b/lincan/src/pc_i03.c
index eb4653c724160a697628ce216b6e915420efb507..cd461af65103bd820554d919bc5ba304eb35edcb 100644 (file)
--- a/lincan/src/pc_i03.c
+++ b/lincan/src/pc_i03.c
@@ -42,7 +42,7 @@
  * we need it global, else we have to change many internal functions.
  * pc-i03_base_addr is initialized in pc-i03_init_chip_data().
  */
-unsigned int pci03_base_addr; 
+unsigned int pci03_base_addr;
 
 /*
  * IO_RANGE is the io-memory range that gets reserved, please adjust according
@@ -58,7 +58,7 @@ unsigned int pci03_base_addr;
  *
  * The function pci03_request_io() is used to reserve the io-memory. If your
  * hardware uses a dedicated memory range as hardware control registers you
- * will have to add the code to reserve this memory as well. 
+ * will have to add the code to reserve this memory as well.
  * %IO_RANGE is the io-memory range that gets reserved, please adjust according
  * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
  * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
@@ -99,8 +99,8 @@ int pci03_release_io(struct candevice_t *candev)
  * pci03_reset - hardware reset routine
  * @candev: Pointer to candevice/board structure
  *
- * The function pci03_reset() is used to give a hardware reset. This is 
- * rather hardware specific so I haven't included example code. Don't forget to 
+ * The function pci03_reset() is used to give a hardware reset. This is
+ * rather hardware specific so I haven't included example code. Don't forget to
  * check the reset status of the chip before returning.
  * Return Value: The function returns zero on success or %-ENODEV on failure
  * File: src/pc-i03.c
@@ -112,15 +112,15 @@ int pci03_reset(struct candevice_t *candev)
        DEBUGMSG("Resetting pc-i03 hardware ...\n");
        pci03_write_register(0x01,pci03_base_addr +
                                0x100); // Write arbitrary data to reset mem
-       udelay(20000);
+       mdelay(20);
 
        pci03_write_register(0x00, pci03_base_addr + SJACR);
-                                                                       
+
        /* Check hardware reset status */
        i=0;
        while ( (pci03_read_register(pci03_base_addr + SJACR) & sjaCR_RR)
                                                                 && (i<=15) ) {
-               udelay(20000);
+               mdelay(20);
                i++;
        }
        if (i>=15) {
@@ -152,7 +152,7 @@ int pci03_reset(struct candevice_t *candev)
  * Return Value: The function always returns zero
  * File: src/pc-i03.c
  */
-int pci03_init_hw_data(struct candevice_t *candev) 
+int pci03_init_hw_data(struct candevice_t *candev)
 {
        candev->res_addr=RESET_ADDR;
        candev->nr_82527_chips=NR_82527;
@@ -184,7 +184,7 @@ int pci03_init_hw_data(struct candevice_t *candev)
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
- * The entry @int_bus_reg holds hardware specific options for the Bus 
+ * The entry @int_bus_reg holds hardware specific options for the Bus
  * Configuration register. Options defined in the %i82527.h file:
  * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
  * Return Value: The function always returns zero
@@ -197,7 +197,7 @@ int pci03_init_chip_data(struct candevice_t *candev, int chipnr)
        candev->chip[chipnr]->chip_base_addr=candev->io_addr;
        candev->chip[chipnr]->clock = 16000000;
        candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
-       candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | 
+       candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL |
                                                        sjaOCR_TX0_HL | sjaOCR_TX1_LZ;
 
        return 0;
@@ -213,7 +213,7 @@ int pci03_init_chip_data(struct candevice_t *candev, int chipnr)
  * CAN chip. In case of the sja1000 there's only one message object but on the
  * i82527 chip there are 15.
  * The code below is for a i82527 chip and initializes the object base addresses
- * The entry @obj_base_addr represents the first memory address of the message 
+ * The entry @obj_base_addr represents the first memory address of the message
  * object. In case of the sja1000 @obj_base_addr is taken the same as the chips
  * base address.
  * Unless the hardware uses a segmented memory map, flags can be set zero.
@@ -223,7 +223,7 @@ int pci03_init_chip_data(struct candevice_t *candev, int chipnr)
 int pci03_init_obj_data(struct canchip_t *chip, int objnr)
 {
        chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
-       
+
        return 0;
 }
 
@@ -231,10 +231,10 @@ int pci03_init_obj_data(struct canchip_t *chip, int objnr)
  * pci03_program_irq - program interrupts
  * @candev: Pointer to candevice/board structure
  *
- * The function pci03_program_irq() is used for hardware that uses 
+ * The function pci03_program_irq() is used for hardware that uses
  * programmable interrupts. If your hardware doesn't use programmable interrupts
- * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and 
- * leave this function unedited. Again this function is hardware specific so 
+ * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
+ * leave this function unedited. Again this function is hardware specific so
  * there's no example code.
  * Return value: The function returns zero on success or %-ENODEV on failure
  * File: src/pc-i03.c