i++;
can_outb(0x01,candev->res_addr);
}
- can_outb(0x00,candev->res_addr);
+ can_outb(0x00,candev->res_addr);
/* Check hardware reset status */
i=0;
can_outb(candev->io_addr+iCPU,candev->io_addr);
while ( (can_inb(candev->io_addr+1)&0x80) && (i<=15) ) {
- udelay(20000);
+ mdelay(20);
i++;
}
if (i>=15) {
DEBUGMSG("Chip0 reset status ok.\n");
return 0;
-}
+}
int smartcan_init_hw_data(struct candevice_t *candev)
{
candev->nr_82527_chips=1;
candev->nr_sja1000_chips=0;
candev->nr_all_chips=1;
-
+
return 0;
}