+ if(i82527_irq_sync_activities(chip, obj)<=0){
+ /* The interrupt has to be cleared anyway */
+ canobj_write_reg(chip,obj,(MVAL_UNC|TXIE_UNC|RXIE_UNC|INTPD_RES),iMSGCTL0);
+
+ /*
+ * Rerun for case, that parallel activity on SMP or fully-preemptive
+ * kernel result in preparation and finished sending of message
+ * between above if and canobj_write_reg.
+ */
+ i82527_irq_sync_activities(chip, obj);
+ }