if (c_can_enable_configuration(pchip))
return -ENODEV;
- clock /=2;
-
/* tseg even = round down, odd = round up */
for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++)
{
if (best_error && (rate/best_error < 10))
{
CANMSG("baud rate %d is not possible with %d Hz clock\n",
- rate, 2*clock);
+ rate, clock);
CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
best_rate, best_brp, best_tseg, tseg1, tseg2);
return -EINVAL;
DEBUGMSG("(c%d)calling c_can_config_irqs(...)\n", pchip->chip_idx);
- /*
- CANMSG("c_can_config_irqs not implemented\n");
- return -ENOSYS;
- */
-
tempreg = c_can_read_reg_w(pchip, CCCR);
//DEBUGMSG("-> CAN Control Register: 0x%.4lx\n",(long)tempreg);
c_can_write_reg_w(pchip, tempreg | (irqs & 0xe), CCCR);
spin_lock( &c_can_if1lock );
-
//loading Message Object in IF1
- if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
+ if (c_can_if1_busycheck(pmsgobj->hostchip))
+ goto error_enodev;
+
c_can_write_reg_w(pmsgobj->hostchip, readMaskCM, CCIF1CM);
c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
+
//setting Message Valid Bit to zero
- if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
+ if (c_can_if1_busycheck(pmsgobj->hostchip))
+ goto error_enodev;
+
c_can_write_reg_w(pmsgobj->hostchip, 0, CCIF1A2);
c_can_write_reg_w(pmsgobj->hostchip, writeMaskCM, CCIF1CM);
c_can_write_reg_w(pmsgobj->hostchip, pmsgobj->object, CCIF1CR);
+
//Configuring Message-Object
- if (c_can_if1_busycheck(pmsgobj->hostchip)) return -ENODEV;
+ /* Only access when the C_CAN controller is idle */
+ if (c_can_if1_busycheck(pmsgobj->hostchip))
+ goto error_enodev;
+
mcreg = c_can_read_reg_w(pmsgobj->hostchip, CCIF1CM);
c_can_write_reg_w(pmsgobj->hostchip,
((mcreg & IFXMC_UMASK) | IFXMC_EOB | IFXMC_RXIE), CCIF1DMC);
#endif
return 0;
+
+error_enodev:
+ CANMSG("Timeout in c_can_if1_busycheck\n");
+ spin_unlock(&c_can_if1lock);
+ return -ENODEV;
+
}
///////////////////////////////////////////////////////////////////////
return -1;
}
- // flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
- // c_can_write_reg_w(pchip, flags, CCCE);
- //
+#ifdef C_CAN_WITH_CCCE
flags = c_can_read_reg_w(pchip, CCCE) | CE_EN;
c_can_write_reg_w(pchip, flags, CCCE);
+#endif
DEBUGMSG("-> ok\n");
#ifdef REGDUMP
return -1;
}
+#ifdef C_CAN_WITH_CCCE
flags = c_can_read_reg_w(pchip, CCCE) & ~CE_EN;
c_can_write_reg_w(pchip, flags, CCCE);
+#endif
DEBUGMSG("-> ok\n");
return 0;
}
+int c_can_attach_to_chip(struct canchip_t *chip)
+{
+ return 0;
+}
+
+int c_can_release_chip(struct canchip_t *chip)
+{
+ int temp;
+
+ temp = c_can_read_reg_w(chip, CCCR);
+
+ /* Disable IRQ generation */
+ c_can_config_irqs(chip, 0);
+
+ temp = c_can_read_reg_w(chip, CCCR);
+
+ /* Power-down C_CAN, except this does nothing in the version 1.2 */
+ c_can_stop_chip(chip);
+
+
+ return 0;
+}
+
///////////////////////////////////////////////////////////////////////
/*
*Check the TxOK bit of the Status Register and resets it afterwards.
(long)(c_can_read_reg_w( pchip, CCTR)));
CANMSG("Baud Rate Presc. Register: 0x%.4lx\n",
(long)(c_can_read_reg_w( pchip, CCBRPE)));
+#ifdef C_CAN_WITH_CCCE
CANMSG("CAN Enable Register: 0x%.4lx\n",
(long)(c_can_read_reg_w( pchip, CCCE)));
+#endif
CANMSG("Transm. Req. 1 Register: 0x%.4lx\n",
(long)(c_can_read_reg_w( pchip, CCTREQ1)));
CANMSG("Transm. Req. 2 Register: 0x%.4lx\n",
CANMSG("------------------------------------\n");
}
+
+void c_can_if1_registerdump(struct canchip_t *pchip)
+{
+ CANMSG("----------------------------------------\n");
+ CANMSG("Error Counting Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCEC)));
+ CANMSG("---------C-CAN IF1 Register Dump--------\n");
+ CANMSG("IF1 Command Req. Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1CR)));
+ CANMSG("IF1 Command Mask Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1CM)));
+ CANMSG("IF1 Mask 1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1M1)));
+ CANMSG("IF1 Mask 2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1M2)));
+ CANMSG("IF1 Arbitration 1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1A1)));
+ CANMSG("IF1 Arbitration 2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1A2)));
+ CANMSG("IF1 Message Control Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1DMC)));
+ CANMSG("IF1 Data A1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1DA1)));
+ CANMSG("IF1 Data A2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1DA2)));
+ CANMSG("IF1 Data B1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1DB1)));
+ CANMSG("IF1 Data B2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w( pchip, CCIF1DB2)));
+}
+
///////////////////////////////////////////////////////////////////////
int c_can_register(struct chipspecops_t *chipspecops)
chipspecops->remote_request=c_can_remote_request;
chipspecops->enable_configuration=c_can_enable_configuration;
chipspecops->disable_configuration=c_can_disable_configuration;
+ chipspecops->attach_to_chip=c_can_attach_to_chip;
+ chipspecops->release_chip=c_can_release_chip;
chipspecops->set_btregs=c_can_set_btregs;
chipspecops->start_chip=c_can_start_chip;
chipspecops->stop_chip=c_can_stop_chip;
int c_can_fill_chipspecops(struct canchip_t *chip)
{
chip->chip_type="c_can";
- chip->max_objects = 32;
+ if(MAX_MSGOBJS >= 32) {
+ chip->max_objects = 32;
+ } else {
+ CANMSG("C_CAN requires 32 message objects per chip,"
+ " but only %d is compiled maximum\n",MAX_MSGOBJS);
+ chip->max_objects = MAX_MSGOBJS;
+ }
c_can_register(chip->chipspecops);
return 0;
}
projects / lincan.git / blobdiff