* Rewritten for new CAN queues by Pavel Pisa - OCERA team member
* email:pisa@cmp.felk.cvut.cz
* This software is released under the GPL-License.
- * Version lincan-0.2 9 Jul 2003
- */
+ * Version lincan-0.3 17 Jun 2004
+ */
/* This file is intended as a bfadcan file for currently unsupported hardware.
* Once you've changed/added the functions specific to your hardware it is
#include "../include/can.h"
#include "../include/can_sysdep.h"
#include "../include/main.h"
-#include "../include/i82527.h"
#include "../include/sja1000p.h"
#define __NO_VERSION__
#include <linux/module.h>
long clock_freq;
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
MODULE_PARM(clock_freq,"i");
+#else
+module_param(clock_freq,int,0);
+#endif
/* cli and sti are not allowed in 2.5.5x SMP kernels */
#ifdef WINDOWED_ACCESS
-static can_spinlock_t bfadcan_win_lock=SPIN_LOCK_UNLOCKED;
+static CAN_DEFINE_SPINLOCK(bfadcan_win_lock);
#endif
/*
#endif
unsigned bfadcan_read_register(unsigned long address);
-void bfadcan_write_register(unsigned char data, unsigned long address);
+void bfadcan_write_register(unsigned data, unsigned long address);
/**
*
* The function bfadcan_request_io() is used to reserve the io-memory. If your
* hardware uses a dedicated memory range as hardware control registers you
- * will have to add the code to reserve this memory as well.
+ * will have to add the code to reserve this memory as well.
* %IO_RANGE is the io-memory range that gets reserved, please adjust according
* your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
* #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
* bfadcan_reset - hardware reset routine
* @candev: Pointer to candevice/board structure
*
- * The function bfadcan_reset() is used to give a hardware reset. This is
- * rather hardware specific so I haven't included example code. Don't forget to
+ * The function bfadcan_reset() is used to give a hardware reset. This is
+ * rather hardware specific so I haven't included example code. Don't forget to
* check the reset status of the chip before returning.
* Return Value: The function returns zero on success or %-ENODEV on failure
* File: src/bfadcan.c
{
int i;
- struct chip_t *chip=candev->chip[0];
+ struct canchip_t *chip=candev->chip[0];
unsigned cdr;
-
- bfadcan_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+
+ bfadcan_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
udelay(1000);
-
+
cdr=bfadcan_read_register(chip->chip_base_addr+SJACDR);
- bfadcan_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ bfadcan_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
bfadcan_write_register(0, chip->chip_base_addr+SJAIER);
i=20;
bfadcan_write_register(0, chip->chip_base_addr+SJAMOD);
- while (bfadcan_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+ while (bfadcan_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
if(!i--) return -ENODEV;
udelay(1000);
bfadcan_write_register(0, chip->chip_base_addr+SJAMOD);
}
cdr=bfadcan_read_register(chip->chip_base_addr+SJACDR);
- bfadcan_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ bfadcan_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
bfadcan_write_register(0, chip->chip_base_addr+SJAIER);
-
+
return 0;
}
* Return Value: The function always returns zero
* File: src/bfadcan.c
*/
-int bfadcan_init_hw_data(struct candevice_t *candev)
+int bfadcan_init_hw_data(struct candevice_t *candev)
{
candev->res_addr=RESET_ADDR;
candev->nr_82527_chips=NR_82527;
return 0;
}
-#define CHIP_TYPE "sja1000p"
/**
* bfadcan_init_chip_data - Initialize chips
* @candev: Pointer to candevice/board structure
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
- * The entry @int_bus_reg holds hardware specific options for the Bus
+ * The entry @int_bus_reg holds hardware specific options for the Bus
* Configuration register. Options defined in the %i82527.h file:
* %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
* The entry @int_cpu_reg holds hardware specific options for the cpu interface
int bfadcan_init_chip_data(struct candevice_t *candev, int chipnr)
{
unsigned int id1, id2;
- candev->chip[chipnr]->chip_type=CHIP_TYPE;
+ sja1000p_fill_chipspecops(candev->chip[chipnr]);
candev->chip[chipnr]->chip_base_addr=candev->io_addr;
candev->chip[chipnr]->clock = clock_freq;
- candev->chip[chipnr]->int_cpu_reg = iCPU_DSC;
- candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
- candev->chip[chipnr]->int_bus_reg = iBUS_CBY;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
- candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL |
- OCR_TX0_LH;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+ candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
id1 = inb(0xe284);
id2 = inb(0xe285);
- CANMSG("can driver ver lincan-0.2, at %04lx, CPLD v%d.%d.%d.%d\n",
+ CANMSG("can driver ver lincan-0.3, at %04lx, CPLD v%d.%d.%d.%d\n",
candev->chip[chipnr]->chip_base_addr,
id1>>4, id1&0x0f, id2>>4, id2&0x0f);
* CAN chip. In case of the sja1000 there's only one message object but on the
* i82527 chip there are 15.
* The code below is for a i82527 chip and initializes the object base addresses
- * The entry @obj_base_addr represents the first memory address of the message
+ * The entry @obj_base_addr represents the first memory address of the message
* object. In case of the sja1000 @obj_base_addr is taken the same as the chips
* base address.
* Unless the hardware uses a segmented memory map, flags can be set zero.
* Return Value: The function always returns zero
* File: src/bfadcan.c
*/
-int bfadcan_init_obj_data(struct chip_t *chip, int objnr)
+int bfadcan_init_obj_data(struct canchip_t *chip, int objnr)
{
chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10;
-
+
return 0;
}
* bfadcan_program_irq - program interrupts
* @candev: Pointer to candevice/board structure
*
- * The function bfadcan_program_irq() is used for hardware that uses
+ * The function bfadcan_program_irq() is used for hardware that uses
* programmable interrupts. If your hardware doesn't use programmable interrupts
- * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
- * leave this function unedited. Again this function is hardware specific so
+ * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
+ * leave this function unedited. Again this function is hardware specific so
* there's no example code.
* Return value: The function returns zero on success or %-ENODEV on failure
* File: src/bfadcan.c
* Return Value: The function does not return a value
* File: src/bfadcan.c
*/
-void bfadcan_write_register(unsigned char data, unsigned long address)
+void bfadcan_write_register(unsigned data, unsigned long address)
{
#ifdef WINDOWED_ACCESS
can_spin_irqflags_t flags;
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