Added prefix sja to all sjaXX_YY register bit-fields definitions.

[lincan.git] / lincan / src / pcccan.c

diff --git a/lincan/src/pcccan.c b/lincan/src/pcccan.c
index ebf315c82e54e685f11e984758b5b4e48d2f9c36..b6790cae9ace4e0e1268ef0410cdeb072067489f 100644 (file)
--- a/lincan/src/pcccan.c
+++ b/lincan/src/pcccan.c
@@ -168,11 +168,11 @@ int pcccan_init_hw_data(struct candevice_t *candev)
  * The @clock entry holds the chip clock value in Hz.
  * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
  * register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
  * The entry @sja_ocr_reg holds hardware specific options for the Output Control
  * register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
@@ -253,7 +253,7 @@ int pcccan_program_irq(struct candevice_t *candev)
  * Return Value: The function does not return a value
  * File: src/pcccan.c
  */
-void pcccan_write_register(unsigned char data, unsigned long address)
+void pcccan_write_register(unsigned data, unsigned long address)
 {
        can_spin_irqflags_t flags;
        can_spin_lock_irqsave(&pcccan_port_lock,flags);