* Rewritten for new CAN queues by Pavel Pisa - OCERA team member
* email:pisa@cmp.felk.cvut.cz
* This software is released under the GPL-License.
- * Version lincan-0.2 9 Jul 2003
+ * Version lincan-0.3 17 Jun 2004
*/
/* This file contains the low level functions for the pcccan-1 card from Gespac.
int pcccan_irq=-1;
unsigned long pcccan_base=0x0;
+static can_spinlock_t pcccan_port_lock=SPIN_LOCK_UNLOCKED;
+
/*
* IO_RANGE is the io-memory range that gets reserved, please adjust according
* your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
int pcccan_init_obj_data(struct chip_t *chip, int objnr)
{
chip->msgobj[objnr]->obj_base_addr=(objnr+1)*0x10;
- chip->msgobj[objnr]->flags=0;
return 0;
}
* Return Value: The function does not return a value
* File: src/pcccan.c
*/
-void pcccan_write_register(unsigned char data, unsigned long address)
+void pcccan_write_register(unsigned data, unsigned long address)
{
- disable_irq(pcccan_irq);
+ can_spin_irqflags_t flags;
+ can_spin_lock_irqsave(&pcccan_port_lock,flags);
outb(address - pcccan_base, pcccan_base+1);
outb(data, pcccan_base+6);
- enable_irq(pcccan_irq);
+ can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
}
/**
unsigned pcccan_read_register(unsigned long address)
{
unsigned ret;
- disable_irq(pcccan_irq);
+ can_spin_irqflags_t flags;
+ can_spin_lock_irqsave(&pcccan_port_lock,flags);
outb(address - pcccan_base, pcccan_base+1);
ret=inb(pcccan_base+2);
- enable_irq(pcccan_irq);
+ can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
return ret;
}