Added prefix sja to all sjaXX_YY register bit-fields definitions.

[lincan.git] / lincan / src / m437.c

diff --git a/lincan/src/m437.c b/lincan/src/m437.c
index 6fa87e7f540a5656b4a741499eedd0bb514de4e0..d6a89ec9cbb34de7dcc5166d5a36ff2e9aabf245 100644 (file)
--- a/lincan/src/m437.c
+++ b/lincan/src/m437.c
@@ -179,11 +179,11 @@ int m437_init_hw_data(struct candevice_t *candev)
  * The @clock entry holds the chip clock value in Hz.
  * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
  * register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
  * The entry @sja_ocr_reg holds hardware specific options for the Output Control
  * register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
@@ -229,7 +229,6 @@ int m437_init_chip_data(struct candevice_t *candev, int chipnr)
 int m437_init_obj_data(struct chip_t *chip, int objnr)
 {
        chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10;
-       chip->msgobj[objnr]->flags=0;
        
        return 0;
 }
@@ -262,7 +261,7 @@ int m437_program_irq(struct candevice_t *candev)
  * Return Value: The function does not return a value
  * File: src/m437.c
  */
-void m437_write_register(unsigned char data, unsigned long address)
+void m437_write_register(unsigned data, unsigned long address)
 {
        writeb(data,base+address);
 }