* Rewritten for new CAN queues by Pavel Pisa - OCERA team member
* email:pisa@cmp.felk.cvut.cz
* This software is released under the GPL-License.
- * Version lincan-0.2 9 Jul 2003
+ * Version lincan-0.3 17 Jun 2004
*/
#include "../include/can.h"
/* Check hardware reset status */
i=0;
- while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & CR_RR)
+ while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
&& (i<=15) ) {
udelay(20000);
i++;
for (chip_nr=0; chip_nr<2; chip_nr++) {
i=0;
while ( (inb(candev->chip[chip_nr]->chip_base_addr +
- SJACR) & CR_RR) && (i<=15) ) {
+ SJACR) & sjaCR_RR) && (i<=15) ) {
udelay(20000);
i++;
}
int i=0,chip_nr=0;
for (i=0; i<4; i++)
- disable_irq(candev->chip[i]->chip_irq);
+ can_disable_irq(candev->chip[i]->chip_irq);
DEBUGMSG("Resetting pccan-q hardware ...\n");
while (i < 100000) {
for (chip_nr=2; chip_nr<4; chip_nr++) {
i=0;
while( (inb(candev->chip[chip_nr]->chip_base_addr +
- SJACR) & CR_RR) && (i<=15) ) {
+ SJACR) & sjaCR_RR) && (i<=15) ) {
udelay(20000);
i++;
}
}
for (i=0; i<4; i++)
- enable_irq(candev->chip[i]->chip_irq);
+ can_enable_irq(candev->chip[i]->chip_irq);
return 0;
}
{
if (!strcmp(candev->hwname,"pccan-q")) {
if (chipnr<2) {
- candev->chip[chipnr]->chip_type="i82527";
+ i82527_fill_chipspecops(candev->chip[chipnr]);
candev->chip[chipnr]->flags = CHIP_SEGMENTED;
candev->chip[chipnr]->int_cpu_reg=iCPU_DSC;
candev->chip[chipnr]->int_clk_reg=iCLK_SL1;
candev->chip[chipnr]->sja_ocr_reg = 0;
}
else{
- candev->chip[chipnr]->chip_type="sja1000";
+ sja1000_fill_chipspecops(candev->chip[chipnr]);
candev->chip[chipnr]->flags = 0;
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
candev->chip[chipnr]->sja_cdr_reg =
- CDR_CLK_OFF;
+ sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg =
- OCR_MODE_NORMAL | OCR_TX0_LH;
+ sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
}
candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr;
}
else {
- candev->chip[chipnr]->chip_type="sja1000";
+ sja1000_fill_chipspecops(candev->chip[chipnr]);
candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x4000+candev->io_addr;
candev->chip[chipnr]->flags = 0;
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CLK_OFF;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg =
- OCR_MODE_NORMAL | OCR_TX0_LH;
+ sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
}
candev->chip[chipnr]->clock = 16000000;
return 0;
}
-int pccan_init_obj_data(struct chip_t *chip, int objnr)
+int pccan_init_obj_data(struct canchip_t *chip, int objnr)
{
if (!strcmp(chip->chip_type,"sja1000")) {
chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
- chip->msgobj[objnr]->flags=0;
- }
+ }
else { /* The spacing for this card is 0x3c0 */
chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10+(int)((objnr+1)/4)*0x3c0;
- chip->msgobj[objnr]->flags=0;
- }
+ }
return 0;
}
return 0;
}
-inline void pccan_write_register(unsigned char data, unsigned long address)
+inline void pccan_write_register(unsigned data, unsigned long address)
{
outb(data,address);
}