Added prefix sja to all sjaXX_YY register bit-fields definitions.

[lincan.git] / lincan / src / aim104.c

diff --git a/lincan/src/aim104.c b/lincan/src/aim104.c
index 1119d613ade61fe96609d1317ba7c49f02f65d0a..ab8bd27813c5cabec1ae608d73e06421c575d8fb 100644 (file)
--- a/lincan/src/aim104.c
+++ b/lincan/src/aim104.c
@@ -85,7 +85,7 @@ int aim104_reset(struct candevice_t *candev)
        /* Check hardware reset status chip 0 */
        i=0;
        while ( (aim104_read_register(candev->io_addr + SJACR) 
-                                                       & CR_RR) && (i<=15) ) {
+                                                       & sjaCR_RR) && (i<=15) ) {
                udelay(20000);
                i++;
        }
@@ -145,11 +145,11 @@ int aim104_init_hw_data(struct candevice_t *candev)
  * The @clock entry holds the chip clock value in Hz.
  * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
  * register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
  * The entry @sja_ocr_reg holds hardware specific options for the Output Control
  * register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.