The first round of I/O space pointers separation.

[lincan.git] / lincan / src / m437.c

diff --git a/lincan/src/m437.c b/lincan/src/m437.c
index eb6a330bd8c54f2ebaf76821cead72bde47e9931..d90db12e3077c07534b23f4ce71cbf725f2adeee 100644 (file)
--- a/lincan/src/m437.c
+++ b/lincan/src/m437.c
@@ -4,7 +4,7 @@
  * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
  * email:pisa@cmp.felk.cvut.cz
  * This software is released under the GPL-License.
- * Version lincan-0.2  9 Jul 2003
+ * Version lincan-0.3  17 Jun 2004
  */ 
 
 /* 
@@ -36,8 +36,6 @@
 #define IO_RANGE 0x100
 
 
-static long base = 0L; 
-
 /**
  * m437_request_io: - reserve io or memory range for can board
  * @candev: pointer to candevice/board which asks for io. Field @io_addr
@@ -60,7 +58,7 @@ int m437_request_io(struct candevice_t *candev)
                return -ENODEV;
        }
 
-       if ( !( base = (long) ioremap( candev->io_addr, IO_RANGE ) ) ) {
+       if ( !( candev->dev_base_addr = ioremap( candev->io_addr, IO_RANGE ) ) ) {
                CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
                can_release_mem_region(candev->io_addr,IO_RANGE);
                return -ENODEV;
@@ -87,7 +85,7 @@ int m437_release_io(struct candevice_t *candev)
        unsigned i;
        
         /* disable IRQ generation */
-        m437_write_register(iCTL_CCE, iCTL);
+        m437_write_register(iCTL_CCE, candev->dev_base_addr+iCTL);
 
        /* clear all message objects */
        for (i=1; i<=15; i++) {
@@ -96,21 +94,21 @@ int m437_release_io(struct candevice_t *candev)
                                RXIE_RES | 
                                TXIE_RES | 
                                MVAL_RES, 
-                               i*0x10+iMSGCTL0);
+                               candev->dev_base_addr+i*0x10+iMSGCTL0);
                m437_write_register(
                                NEWD_RES | 
                                MLST_RES | 
                                CPUU_RES | 
                                TXRQ_RES | 
                                RMPD_RES, 
-                               i*0x10+iMSGCTL1);
+                               candev->dev_base_addr+i*0x10+iMSGCTL1);
        }
        
        /* power down i82527 */
-       m437_write_register(iCPU_PWD, iCPU);
+       m437_write_register(iCPU_PWD, candev->dev_base_addr+iCPU);
        
        /* release I/O memory mapping */
-       iounmap((void*)base);
+       iounmap(candev->dev_base_addr);
 
        can_release_mem_region(candev->io_addr,IO_RANGE);
 
@@ -163,7 +161,6 @@ int m437_init_hw_data(struct candevice_t *candev)
        return 0;
 }
 
-#define CHIP_TYPE "i82527"
 /**
  * m437_init_chip_data - Initialize chips
  * @candev: Pointer to candevice/board structure
@@ -179,11 +176,11 @@ int m437_init_hw_data(struct candevice_t *candev)
  * The @clock entry holds the chip clock value in Hz.
  * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
  * register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
  * The entry @sja_ocr_reg holds hardware specific options for the Output Control
  * register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
@@ -198,8 +195,8 @@ int m437_init_hw_data(struct candevice_t *candev)
  */
 int m437_init_chip_data(struct candevice_t *candev, int chipnr)
 {
-       candev->chip[chipnr]->chip_type=CHIP_TYPE;
-       candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+       i82527_fill_chipspecops(candev->chip[chipnr]);
+       candev->chip[chipnr]->chip_base_addr=candev->dev_base_addr;
        candev->chip[chipnr]->clock = 16000000;
        candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_CEN;
        candev->chip[chipnr]->int_clk_reg = 
@@ -226,7 +223,7 @@ int m437_init_chip_data(struct candevice_t *candev, int chipnr)
  * Return Value: The function always returns zero
  * File: src/m437.c
  */
-int m437_init_obj_data(struct chip_t *chip, int objnr)
+int m437_init_obj_data(struct canchip_t *chip, int objnr)
 {
        chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10;
        
@@ -261,9 +258,9 @@ int m437_program_irq(struct candevice_t *candev)
  * Return Value: The function does not return a value
  * File: src/m437.c
  */
-void m437_write_register(unsigned data, unsigned long address)
+void m437_write_register(unsigned data, can_ioptr_t address)
 {
-       writeb(data,base+address);
+       can_writeb(data,address);
 }
 
 /**
@@ -276,9 +273,9 @@ void m437_write_register(unsigned data, unsigned long address)
  * Return Value: The function returns the value stored in @address
  * File: src/m437.c
  */
-unsigned m437_read_register(unsigned long address)
+unsigned m437_read_register(can_ioptr_t address)
 {
-       return readb(base+address);
+       return can_readb(address);
 }
 
 /* !!! Don't change this function !!! */