* Version lincan-0.3 17 Jun 2004
*/
-int sja1000_enable_configuration(struct chip_t *chip);
-int sja1000_disable_configuration(struct chip_t *chip);
-int sja1000_chip_config(struct chip_t *chip);
-int sja1000_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask);
-int sja1000_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
+int sja1000_enable_configuration(struct canchip_t *chip);
+int sja1000_disable_configuration(struct canchip_t *chip);
+int sja1000_chip_config(struct canchip_t *chip);
+int sja1000_standard_mask(struct canchip_t *chip, unsigned short code, unsigned short mask);
+int sja1000_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
int sampl_pt, int flags);
-int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj);
-int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
+int sja1000_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj);
+int sja1000_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg);
-int sja1000_send_msg(struct chip_t *chip, struct msgobj_t *obj,
+int sja1000_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg);
-int sja1000_check_tx_stat(struct chip_t *chip);
-int sja1000_set_btregs(struct chip_t *chip, unsigned short btr0,
+int sja1000_check_tx_stat(struct canchip_t *chip);
+int sja1000_set_btregs(struct canchip_t *chip, unsigned short btr0,
unsigned short btr1);
-int sja1000_start_chip(struct chip_t *chip);
-int sja1000_stop_chip(struct chip_t *chip);
-can_irqreturn_t sja1000_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
+int sja1000_start_chip(struct canchip_t *chip);
+int sja1000_stop_chip(struct canchip_t *chip);
+int sja1000_irq_handler(int irq, struct canchip_t *chip);
+int sja1000_fill_chipspecops(struct canchip_t *chip);
/* BasicCAN mode address map */
#define SJACR 0x00 /* Control register */
/* Clock Divider Register */
enum sja1000_CDR {
/* f_out = f_osc/(2*(CDR[2:0]+1)) or f_osc if CDR[2:0]==7 */
+ sjaCDR_CLKOUT_DIV1 = 7,
+ sjaCDR_CLKOUT_DIV2 = 0,
+ sjaCDR_CLKOUT_DIV4 = 1,
+ sjaCDR_CLKOUT_DIV6 = 2,
+ sjaCDR_CLKOUT_DIV8 = 3,
+ sjaCDR_CLKOUT_DIV10 = 4,
+ sjaCDR_CLKOUT_DIV12 = 5,
+ sjaCDR_CLKOUT_DIV14 = 6,
sjaCDR_CLKOUT_MASK = 7,
sjaCDR_CLK_OFF = 1<<3, // Clock Off
sjaCDR_RXINPEN = 1<<5, // TX1 output is RX irq output