Added prefix sja to all sjaXX_YY register bit-fields definitions.

[lincan.git] / lincan / src / pc_i03.c

diff --git a/lincan/src/pc_i03.c b/lincan/src/pc_i03.c
index c7b3863c732c916b20e37070b44c20b360c6d670..5340e93d172a1787c7aba5b1f1f5dc49ce53d35d 100644 (file)
--- a/lincan/src/pc_i03.c
+++ b/lincan/src/pc_i03.c
@@ -93,7 +93,7 @@ int pci03_reset(struct candevice_t *candev)
                                                                        
        /* Check hardware reset status */
        i=0;
-       while ( (pci03_read_register(pci03_base_addr + SJACR) & CR_RR)
+       while ( (pci03_read_register(pci03_base_addr + SJACR) & sjaCR_RR)
                                                                 && (i<=15) ) {
                udelay(20000);
                i++;
@@ -152,11 +152,11 @@ int pci03_init_hw_data(struct candevice_t *candev)
  * The @clock entry holds the chip clock value in Hz.
  * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
  * register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
  * The entry @sja_ocr_reg holds hardware specific options for the Output Control
  * register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
  * The entry @int_clk_reg holds hardware specific options for the Clock Out
  * register. Options defined in the %i82527.h file:
  * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
@@ -172,9 +172,9 @@ int pci03_init_chip_data(struct candevice_t *candev, int chipnr)
        candev->chip[chipnr]->chip_type=CHIP_TYPE;
        candev->chip[chipnr]->chip_base_addr=candev->io_addr;
        candev->chip[chipnr]->clock = 16000000;
-       candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
-       candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL | 
-                                                       OCR_TX0_HL | OCR_TX1_LZ;
+       candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+       candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | 
+                                                       sjaOCR_TX0_HL | sjaOCR_TX1_LZ;
 
        return 0;
 }