+ pita2_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
+ if (!(candev->dev_base_addr = (long) ioremap(pita2_addr,
+ pci_resource_len(candev->sysdevptr.pcidev,0)))) {
+ CANMSG("Unable to access I/O memory at: 0x%lx\n", pita2_addr);
+ goto error_ioremap_pita2;
+ }
+
+ io_addr=pci_resource_start(candev->sysdevptr.pcidev,1);;
+ if (!(candev->io_addr = (long) ioremap(io_addr,
+ pci_resource_len(candev->sysdevptr.pcidev,1)))) {
+ CANMSG("Unable to access I/O memory at: 0x%lx\n", io_addr);
+ goto error_ioremap_io;
+ }
+
+ candev->res_addr=candev->io_addr;
+
+ /*
+ * this is redundant with chip initialization, but remap address
+ * can change when resources are temporarily released
+ */
+ for(i=0;i<candev->nr_all_chips;i++) {
+ struct canchip_t *chip=candev->chip[i];
+ if(!chip) continue;
+ chip->chip_base_addr = candev->io_addr+
+ 0x400 + i*EMS_CPCPCI_BYTES_PER_CIRCUIT;
+ if(!chip->msgobj[0]) continue;
+ chip->msgobj[0]->obj_base_addr=chip->chip_base_addr;
+ }
+
+ /* Configure PITA-2 parallel interface */
+ writel(PITA2_MISC_CONFIG, candev->dev_base_addr + PITA2_MISC);
+