-/* sja1000.c
- * Linux CAN-bus device driver.
- * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
- * Changed for PeliCan mode SJA1000 by Tomasz Motylewski (BFAD GmbH)
- * T.Motylewski@bfad.de
- * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
- * email:pisa@cmp.felk.cvut.cz
- * This software is released under the GPL-License.
- * Version lincan-0.2 9 Jul 2003
- */
+/**************************************************************************/
+/* File: sja1000p.c - Philips/NXP SJA1000 chip PeliCanCAN mode support */
+/* */
+/* LinCAN - (Not only) Linux CAN bus driver */
+/* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
+/* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
+/* Copyright (C) 2004-2005 Tomasz Motylewski (BFAD GmbH) */
+/* Funded by OCERA and FRESCOR IST projects */
+/* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
+/* */
+/* LinCAN is free software; you can redistribute it and/or modify it */
+/* under terms of the GNU General Public License as published by the */
+/* Free Software Foundation; either version 2, or (at your option) any */
+/* later version. LinCAN is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
+/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
+/* General Public License for more details. You should have received a */
+/* copy of the GNU General Public License along with LinCAN; see file */
+/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
+/* Cambridge, MA 02139, USA. */
+/* */
+/* To allow use of LinCAN in the compact embedded systems firmware */
+/* and RT-executives (RTEMS for example), main authors agree with next */
+/* special exception: */
+/* */
+/* Including LinCAN header files in a file, instantiating LinCAN generics */
+/* or templates, or linking other files with LinCAN objects to produce */
+/* an application image/executable, does not by itself cause the */
+/* resulting application image/executable to be covered by */
+/* the GNU General Public License. */
+/* This exception does not however invalidate any other reasons */
+/* why the executable file might be covered by the GNU Public License. */
+/* Publication of enhanced or derived LinCAN files is required although. */
+/**************************************************************************/
#include "../include/can.h"
#include "../include/can_sysdep.h"
#include "../include/main.h"
#include "../include/sja1000p.h"
+#ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
+
+static const char *sja1000_ecc_errc_str[]={
+ "bit error",
+ "form error",
+ "stuff error",
+ "other type of error"
+};
+
+static const char *sja1000_ecc_seg_str[]={
+ "?0?",
+ "?1?",
+ "ID.28 to ID.21",
+ "start of frame",
+ "bit SRTR",
+ "bit IDE",
+ "ID.20 to ID.18",
+ "ID.17 to ID.13",
+ "CRC sequence",
+ "reserved bit 0",
+ "data field",
+ "data length code",
+ "bit RTR",
+ "reserved bit 1",
+ "ID.4 to ID.0",
+ "ID.12 to ID.5",
+ "?16?"
+ "active error flag",
+ "intermission",
+ "tolerate dominant bits",
+ "?20?",
+ "?21?",
+ "passive error flag",
+ "error delimiter",
+ "CRC delimiter",
+ "acknowledge slot",
+ "end of frame",
+ "acknowledge delimiter",
+ "overload flag",
+ "?29?",
+ "?30?",
+ "?31?"
+};
+
+#endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
+
+static int sja1000_report_error_limit_counter;
+
+static void sja1000_report_error(struct canchip_t *chip,
+ unsigned sr, unsigned ir, unsigned ecc)
+{
+ if(sja1000_report_error_limit_counter>=100)
+ return;
+
+ CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
+ sr, ir, ecc);
+
+ sja1000_report_error_limit_counter+=10;
+
+ if(sja1000_report_error_limit_counter>=100){
+ sja1000_report_error_limit_counter+=10;
+ CANMSG("Error: too many errors, reporting disabled\n");
+ return;
+ }
+
+#ifdef CONFIG_OC_LINCAN_DETAILED_ERRORS
+ CANMSG("SR: BS=%c ES=%c TS=%c RS=%c TCS=%c TBS=%c DOS=%c RBS=%c\n",
+ sr&sjaSR_BS?'1':'0',sr&sjaSR_ES?'1':'0',
+ sr&sjaSR_TS?'1':'0',sr&sjaSR_RS?'1':'0',
+ sr&sjaSR_TCS?'1':'0',sr&sjaSR_TBS?'1':'0',
+ sr&sjaSR_DOS?'1':'0',sr&sjaSR_RBS?'1':'0');
+ CANMSG("IR: BEI=%c ALI=%c EPI=%c WUI=%c DOI=%c EI=%c TI=%c RI=%c\n",
+ sr&sjaIR_BEI?'1':'0',sr&sjaIR_ALI?'1':'0',
+ sr&sjaIR_EPI?'1':'0',sr&sjaIR_WUI?'1':'0',
+ sr&sjaIR_DOI?'1':'0',sr&sjaIR_EI?'1':'0',
+ sr&sjaIR_TI?'1':'0',sr&sjaIR_RI?'1':'0');
+ if((sr&sjaIR_EI) || 1){
+ CANMSG("EI: %s %s %s\n",
+ sja1000_ecc_errc_str[(ecc&(sjaECC_ERCC1|sjaECC_ERCC0))/sjaECC_ERCC0],
+ ecc&sjaECC_DIR?"RX":"TX",
+ sja1000_ecc_seg_str[ecc&sjaECC_SEG_M]
+ );
+ }
+#endif /*CONFIG_OC_LINCAN_DETAILED_ERRORS*/
+}
+
+
/**
* sja1000p_enable_configuration - enable chip configuration mode
* @chip: pointer to chip state structure
*/
-int sja1000p_enable_configuration(struct chip_t *chip)
+int sja1000p_enable_configuration(struct canchip_t *chip)
{
int i=0;
enum sja1000_PeliCAN_MOD flags;
- disable_irq(chip->chip_irq);
+ can_disable_irq(chip->chip_irq);
flags=can_read_reg(chip,SJAMOD);
- while ((!(flags & MOD_RM)) && (i<=10)) {
- can_write_reg(chip, MOD_RM, SJAMOD);
-// TODO: configurable MOD_AFM (32/16 bit acceptance filter)
-// config MOD_LOM (listen only)
+ while ((!(flags & sjaMOD_RM)) && (i<=10)) {
+ can_write_reg(chip, sjaMOD_RM, SJAMOD);
+// TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
+// config sjaMOD_LOM (listen only)
udelay(100);
i++;
flags=can_read_reg(chip, SJAMOD);
}
if (i>=10) {
CANMSG("Reset error\n");
- enable_irq(chip->chip_irq);
+ can_enable_irq(chip->chip_irq);
return -ENODEV;
}
* sja1000p_disable_configuration - disable chip configuration mode
* @chip: pointer to chip state structure
*/
-int sja1000p_disable_configuration(struct chip_t *chip)
+int sja1000p_disable_configuration(struct canchip_t *chip)
{
int i=0;
enum sja1000_PeliCAN_MOD flags;
flags=can_read_reg(chip,SJAMOD);
- while ( (flags & MOD_RM) && (i<=50) ) {
+ while ( (flags & sjaMOD_RM) && (i<=50) ) {
// could be as long as 11*128 bit times after buss-off
can_write_reg(chip, 0, SJAMOD);
-// TODO: configurable MOD_AFM (32/16 bit acceptance filter)
-// config MOD_LOM (listen only)
+// TODO: configurable sjaMOD_AFM (32/16 bit acceptance filter)
+// config sjaMOD_LOM (listen only)
udelay(100);
i++;
flags=can_read_reg(chip, SJAMOD);
return -ENODEV;
}
- enable_irq(chip->chip_irq);
+ can_enable_irq(chip->chip_irq);
return 0;
}
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_chip_config(struct chip_t *chip)
+int sja1000p_chip_config(struct canchip_t *chip)
{
int i;
unsigned char n, r;
return -ENODEV;
/* Set mode, clock out, comparator */
- can_write_reg(chip,CDR_PELICAN|chip->sja_cdr_reg,SJACDR);
+ can_write_reg(chip,sjaCDR_PELICAN|chip->sja_cdr_reg,SJACDR);
+
+ /* Ensure, that interrupts are disabled even on the chip level now */
+ can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
+
/* Set driver output configuration */
can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
return -ENODEV;
/* Enable hardware interrupts */
- can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER);
+ can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER);
sja1000p_disable_configuration(chip);
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_extended_mask(struct chip_t *chip, unsigned long code, unsigned long mask)
+int sja1000p_extended_mask(struct canchip_t *chip, unsigned long code, unsigned long mask)
{
int i;
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
+int sja1000p_baud_rate(struct canchip_t *chip, int rate, int clock, int sjw,
int sampl_pt, int flags)
{
int best_error = 1000000000, error;
clock /=2;
/* tseg even = round down, odd = round up */
- for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
+ for (tseg=(0+0+2)*2; tseg<=(sjaMAX_TSEG2+sjaMAX_TSEG1+2)*2+1; tseg++) {
brp = clock/((1+tseg/2)*rate)+tseg%2;
if (brp == 0 || brp > 64)
continue;
tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
if (tseg2 < 0)
tseg2 = 0;
- if (tseg2 > MAX_TSEG2)
- tseg2 = MAX_TSEG2;
+ if (tseg2 > sjaMAX_TSEG2)
+ tseg2 = sjaMAX_TSEG2;
tseg1 = best_tseg-tseg2-2;
- if (tseg1>MAX_TSEG1) {
- tseg1 = MAX_TSEG1;
+ if (tseg1>sjaMAX_TSEG1) {
+ tseg1 = sjaMAX_TSEG1;
tseg2 = best_tseg-tseg1-2;
}
*
* File: src/sja1000p.c
*/
-void sja1000p_read(struct chip_t *chip, struct msgobj_t *obj) {
+void sja1000p_read(struct canchip_t *chip, struct msgobj_t *obj) {
int i, flags, len, datastart;
do {
flags = can_read_reg(chip,SJAFRM);
- if(flags&FRM_FF) {
+ if(flags&sjaFRM_FF) {
obj->rx_msg.id =
(can_read_reg(chip,SJAID0)<<21) +
(can_read_reg(chip,SJAID1)<<13) +
datastart = SJADATS;
}
obj->rx_msg.flags =
- ((flags & FRM_RTR) ? MSG_RTR : 0) |
- ((flags & FRM_FF) ? MSG_EXT : 0);
- len = flags & FRM_DLC_M;
+ ((flags & sjaFRM_RTR) ? MSG_RTR : 0) |
+ ((flags & sjaFRM_FF) ? MSG_EXT : 0);
+ len = flags & sjaFRM_DLC_M;
obj->rx_msg.length = len;
if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
for(i=0; i< len; i++) {
obj->rx_msg.data[i]=can_read_reg(chip,datastart+i);
}
+ /* fill CAN message timestamp */
+ can_filltimestamp(&obj->rx_msg.timestamp);
+
canque_filter_msg2edges(obj->qends, &obj->rx_msg);
- can_write_reg(chip, CMR_RRB, SJACMR);
+ can_write_reg(chip, sjaCMR_RRB, SJACMR);
- } while (can_read_reg(chip, SJASR) & SR_RBS);
+ } while (can_read_reg(chip, SJASR) & sjaSR_RBS);
}
/**
* Positive value indicates immediate reception of message.
* File: src/sja1000p.c
*/
-int sja1000p_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
+int sja1000p_pre_read_config(struct canchip_t *chip, struct msgobj_t *obj)
{
int status;
status=can_read_reg(chip,SJASR);
- if(status & SR_BS) {
+ if(status & sjaSR_BS) {
/* Try to recover from error condition */
DEBUGMSG("sja1000p_pre_read_config bus-off recover 0x%x\n",status);
sja1000p_enable_configuration(chip);
sja1000p_disable_configuration(chip);
}
- if (!(status&SR_RBS)) {
+ if (!(status&sjaSR_RBS)) {
return 0;
}
- can_write_reg(chip, DISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
+ can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER); //disable interrupts for a moment
sja1000p_read(chip, obj);
- can_write_reg(chip, ENABLE_INTERRUPTS, SJAIER); //enable interrupts
+ can_write_reg(chip, sjaENABLE_INTERRUPTS, SJAIER); //enable interrupts
return 1;
}
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
+int sja1000p_pre_write_config(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg)
{
int i=0;
int len;
/* Wait until Transmit Buffer Status is released */
- while ( !((status=can_read_reg(chip, SJASR)) & SR_TBS) &&
+ while ( !((status=can_read_reg(chip, SJASR)) & sjaSR_TBS) &&
i++<MAX_TRANSMIT_WAIT_LOOPS) {
udelay(i);
}
- if(status & SR_BS) {
+ if(status & sjaSR_BS) {
/* Try to recover from error condition */
DEBUGMSG("sja1000p_pre_write_config bus-off recover 0x%x\n",status);
sja1000p_enable_configuration(chip);
can_read_reg(chip, SJAECC);
sja1000p_disable_configuration(chip);
}
- if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
+ if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
CANMSG("Transmit timed out, cancelling\n");
// here we should check if there is no write/select waiting for this
// transmit. If so, set error ret and wake up.
-// CHECKME: if we do not disable IER_TIE (TX IRQ) here we get interrupt
+// CHECKME: if we do not disable sjaIER_TIE (TX IRQ) here we get interrupt
// immediately
- can_write_reg(chip, CMR_AT, SJACMR);
+ can_write_reg(chip, sjaCMR_AT, SJACMR);
i=0;
- while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
+ while ( !(can_read_reg(chip, SJASR) & sjaSR_TBS) &&
i++<MAX_TRANSMIT_WAIT_LOOPS) {
udelay(i);
}
- if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
+ if (!(can_read_reg(chip, SJASR) & sjaSR_TBS)) {
CANMSG("Could not cancel, please reset\n");
return -EIO;
}
}
len = msg->length;
if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
- /* len &= FRM_DLC_M; ensured by above condition already */
- can_write_reg(chip, ((msg->flags&MSG_EXT)?FRM_FF:0) |
- ((msg->flags & MSG_RTR) ? FRM_RTR : 0) | len, SJAFRM);
+ /* len &= sjaFRM_DLC_M; ensured by above condition already */
+ can_write_reg(chip, ((msg->flags&MSG_EXT)?sjaFRM_FF:0) |
+ ((msg->flags & MSG_RTR) ? sjaFRM_RTR : 0) | len, SJAFRM);
if(msg->flags&MSG_EXT) {
id=msg->id<<3;
can_write_reg(chip, id & 0xff, SJAID3);
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_send_msg(struct chip_t *chip, struct msgobj_t *obj,
+int sja1000p_send_msg(struct canchip_t *chip, struct msgobj_t *obj,
struct canmsg_t *msg)
{
- can_write_reg(chip, CMR_TR, SJACMR);
+ can_write_reg(chip, sjaCMR_TR, SJACMR);
return 0;
}
* Zero value indicates finishing of all issued transmission requests.
* File: src/sja1000p.c
*/
-int sja1000p_check_tx_stat(struct chip_t *chip)
+int sja1000p_check_tx_stat(struct canchip_t *chip)
{
- if (can_read_reg(chip,SJASR) & SR_TCS)
+ if (can_read_reg(chip,SJASR) & sjaSR_TCS)
return 0;
else
return 1;
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_set_btregs(struct chip_t *chip, unsigned short btr0,
+int sja1000p_set_btregs(struct canchip_t *chip, unsigned short btr0,
unsigned short btr1)
{
if (sja1000p_enable_configuration(chip))
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_start_chip(struct chip_t *chip)
+int sja1000p_start_chip(struct canchip_t *chip)
{
enum sja1000_PeliCAN_MOD flags;
- flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
+ flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
can_write_reg(chip, flags, SJAMOD);
+ sja1000_report_error_limit_counter=0;
+
return 0;
}
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_stop_chip(struct chip_t *chip)
+int sja1000p_stop_chip(struct canchip_t *chip)
{
enum sja1000_PeliCAN_MOD flags;
- flags = can_read_reg(chip, SJAMOD) & (MOD_LOM|MOD_STM|MOD_AFM|MOD_SM);
- can_write_reg(chip, flags|MOD_RM, SJAMOD);
+ flags = can_read_reg(chip, SJAMOD) & (sjaMOD_LOM|sjaMOD_STM|sjaMOD_AFM|sjaMOD_SM);
+ can_write_reg(chip, flags|sjaMOD_RM, SJAMOD);
return 0;
}
+/**
+ * sja1000p_attach_to_chip: - attaches to the chip, setups registers and state
+ * @chip: pointer to chip state structure
+ *
+ * Return Value: negative value reports error.
+ * File: src/sja1000p.c
+ */
+int sja1000p_attach_to_chip(struct canchip_t *chip)
+{
+ return 0;
+}
+
+/**
+ * sja1000p_release_chip: - called before chip structure removal if %CHIP_ATTACHED is set
+ * @chip: pointer to chip state structure
+ *
+ * Return Value: negative value reports error.
+ * File: src/sja1000p.c
+ */
+int sja1000p_release_chip(struct canchip_t *chip)
+{
+ sja1000p_stop_chip(chip);
+ can_write_reg(chip, sjaDISABLE_INTERRUPTS, SJAIER);
+
+ return 0;
+}
/**
* sja1000p_remote_request: - configures message object and asks for RTR message
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_remote_request(struct chip_t *chip, struct msgobj_t *obj)
+int sja1000p_remote_request(struct canchip_t *chip, struct msgobj_t *obj)
{
CANMSG("sja1000p_remote_request not implemented\n");
return -ENOSYS;
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_standard_mask(struct chip_t *chip, unsigned short code,
+int sja1000p_standard_mask(struct canchip_t *chip, unsigned short code,
unsigned short mask)
{
CANMSG("sja1000p_standard_mask not implemented\n");
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_clear_objects(struct chip_t *chip)
+int sja1000p_clear_objects(struct canchip_t *chip)
{
CANMSG("sja1000p_clear_objects not implemented\n");
return -ENOSYS;
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_config_irqs(struct chip_t *chip, short irqs)
+int sja1000p_config_irqs(struct canchip_t *chip, short irqs)
{
CANMSG("sja1000p_config_irqs not implemented\n");
return -ENOSYS;
* sja1000p_irq_write_handler() for transmit events.
* File: src/sja1000p.c
*/
-void sja1000p_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
+void sja1000p_irq_write_handler(struct canchip_t *chip, struct msgobj_t *obj)
{
int cmd;
if(obj->tx_slot){
/* Do local transmitted message distribution if enabled */
if (processlocal){
+ /* fill CAN message timestamp */
+ can_filltimestamp(&obj->tx_slot->msg.timestamp);
+
obj->tx_slot->msg.flags |= MSG_LOCAL;
canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
}
obj->tx_slot=NULL;
}
+ can_msgobj_clear_fl(obj,TX_PENDING);
cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
if(cmd<0)
return;
+ can_msgobj_set_fl(obj,TX_PENDING);
if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
obj->ret = -1;
/**
* sja1000p_irq_handler: - interrupt service routine
* @irq: interrupt vector number, this value is system specific
- * @dev_id: driver private pointer registered at time of request_irq() call.
- * The CAN driver uses this pointer to store relationship of interrupt
- * to chip state structure - @struct chip_t
- * @regs: system dependent value pointing to registers stored in exception frame
+ * @chip: pointer to chip state structure
*
* Interrupt handler is activated when state of CAN controller chip changes,
* there is message to be read or there is more space for new messages or
* message queues.
* File: src/sja1000p.c
*/
-irqreturn_t sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+int sja1000p_irq_handler(int irq, struct canchip_t *chip)
{
int irq_register, status, error_code;
- struct chip_t *chip=(struct chip_t *)dev_id;
struct msgobj_t *obj=chip->msgobj[0];
+ int loop_cnt=CHIP_MAX_IRQLOOP;
irq_register=can_read_reg(chip,SJAIR);
// DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
// DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
// can_read_reg(chip,SJASR));
- if ((irq_register & (IR_BEI|IR_EPI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
- return IRQ_NONE;
+ if ((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_TI|sjaIR_RI)) == 0)
+ return CANCHIP_IRQ_NONE;
- if(!obj->flags & OBJ_BUFFERS_ALLOCATED) {
- CANMSG("sja1000p_irq_handler: called with device closed, irq_register 0x%02x\n", irq_register);
- return IRQ_NONE;
+ if(!(chip->flags&CHIP_CONFIGURED)) {
+ CANMSG("sja1000p_irq_handler: called for non-configured device, irq_register 0x%02x\n", irq_register);
+ return CANCHIP_IRQ_NONE;
}
- if ((irq_register & IR_RI) != 0) {
- DEBUGMSG("sja1000_irq_handler: RI\n");
- sja1000p_read(chip,obj);
- obj->ret = 0;
- }
- if ((irq_register & IR_TI) != 0) {
- DEBUGMSG("sja1000_irq_handler: TI\n");
- obj->ret = 0;
- set_bit(OBJ_TX_REQUEST,&obj->flags);
- while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
- clear_bit(OBJ_TX_REQUEST,&obj->flags);
-
- if (can_read_reg(chip, SJASR) & SR_TBS)
- sja1000p_irq_write_handler(chip, obj);
-
- clear_bit(OBJ_TX_LOCK,&obj->flags);
- if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
- DEBUGMSG("TX looping in sja1000_irq_handler\n");
- }
- }
- if ((irq_register & (IR_EI|IR_BEI|IR_EPI|IR_DOI)) != 0) {
- // Some error happened
- status=can_read_reg(chip,SJASR);
- error_code=can_read_reg(chip,SJAECC);
- CANMSG("Error: status register: 0x%x irq_register: 0x%02x error: 0x%02x\n",
- status, irq_register, error_code);
-// FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
-// Reset flag set to 0 if chip is already off the bus. Full state report
- obj->ret=-1;
-
- if(error_code == 0xd9) {
- obj->ret= -ENXIO;
- /* no such device or address - no ACK received */
+ status=can_read_reg(chip,SJASR);
+
+ do {
+
+ if(!loop_cnt--) {
+ CANMSG("sja1000p_irq_handler IRQ %d stuck\n",irq);
+ return CANCHIP_IRQ_STUCK;
}
- if(obj->tx_retry_cnt++>MAX_RETR) {
- can_write_reg(chip, CMR_AT, SJACMR); // cancel any transmition
- obj->tx_retry_cnt = 0;
+
+ /* (irq_register & sjaIR_RI) */
+ /* old variant using SJAIR, collides with intended use with irq_accept */
+ if (status & sjaSR_RBS) {
+ DEBUGMSG("sja1000_irq_handler: RI or RBS\n");
+ sja1000p_read(chip,obj);
+ obj->ret = 0;
}
- if(status&SR_BS) {
- CANMSG("bus-off, resetting sja1000p\n");
- can_write_reg(chip, 0, SJAMOD);
+
+ /* (irq_register & sjaIR_TI) */
+ /* old variant using SJAIR, collides with intended use with irq_accept */
+ if (((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING))||
+ (can_msgobj_test_fl(obj,TX_REQUEST))) {
+ DEBUGMSG("sja1000_irq_handler: TI or TX_PENDING and TBS\n");
+ obj->ret = 0;
+ can_msgobj_set_fl(obj,TX_REQUEST);
+ while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
+ can_msgobj_clear_fl(obj,TX_REQUEST);
+
+ if (can_read_reg(chip, SJASR) & sjaSR_TBS)
+ sja1000p_irq_write_handler(chip, obj);
+
+ can_msgobj_clear_fl(obj,TX_LOCK);
+ if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
+ DEBUGMSG("TX looping in sja1000_irq_handler\n");
+ }
}
+ if ((irq_register & (sjaIR_EI|sjaIR_BEI|sjaIR_EPI|sjaIR_DOI)) != 0) {
+ // Some error happened
+ error_code=can_read_reg(chip,SJAECC);
+ sja1000_report_error(chip, status, irq_register, error_code);
+// FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
+// Reset flag set to 0 if chip is already off the bus. Full state report
+ obj->ret=-1;
- if(obj->tx_slot){
- canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
- /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
- obj->tx_slot=NULL;*/
+ if(error_code == 0xd9) {
+ obj->ret= -ENXIO;
+ /* no such device or address - no ACK received */
+ }
+ if(obj->tx_retry_cnt++>MAX_RETR) {
+ can_write_reg(chip, sjaCMR_AT, SJACMR); // cancel any transmition
+ obj->tx_retry_cnt = 0;
+ }
+ if(status&sjaSR_BS) {
+ CANMSG("bus-off, resetting sja1000p\n");
+ can_write_reg(chip, 0, SJAMOD);
+ }
+
+ if(obj->tx_slot){
+ canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
+ /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
+ obj->tx_slot=NULL;*/
+ }
+
+ } else {
+ if(sja1000_report_error_limit_counter)
+ sja1000_report_error_limit_counter--;
+ obj->tx_retry_cnt=0;
}
- } else {
- obj->tx_retry_cnt=0;
- }
+ irq_register=can_read_reg(chip,SJAIR);
- return IRQ_HANDLED;
+ status=can_read_reg(chip,SJASR);
+
+ if(((status & sjaSR_TBS) && can_msgobj_test_fl(obj,TX_PENDING)) ||
+ (irq_register & sjaIR_TI))
+ can_msgobj_set_fl(obj,TX_REQUEST);
+
+ } while((irq_register & (sjaIR_BEI|sjaIR_EPI|sjaIR_DOI|sjaIR_EI|sjaIR_RI)) ||
+ (can_msgobj_test_fl(obj,TX_REQUEST) && !can_msgobj_test_fl(obj,TX_LOCK)) ||
+ (status & sjaSR_RBS));
+
+ return CANCHIP_IRQ_HANDLED;
}
/**
* @chip: pointer to chip state structure
* @obj: pointer to message object structure
*
+ * Function is responsible for initiating message transmition.
+ * It is responsible for clearing of object TX_REQUEST flag
+ *
* Return Value: negative value reports error.
* File: src/sja1000p.c
*/
-int sja1000p_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
+int sja1000p_wakeup_tx(struct canchip_t *chip, struct msgobj_t *obj)
{
- /* dummy lock to prevent preemption fully portable way */
- can_spinlock_t dummy_lock;
- /* preempt_disable() */
- can_spin_lock_init(&dummy_lock);
- can_spin_lock(&dummy_lock);
+ can_preempt_disable();
- set_bit(OBJ_TX_REQUEST,&obj->flags);
- while(!test_and_set_bit(OBJ_TX_LOCK,&obj->flags)){
- clear_bit(OBJ_TX_REQUEST,&obj->flags);
+ can_msgobj_set_fl(obj,TX_PENDING);
+ can_msgobj_set_fl(obj,TX_REQUEST);
+ while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
+ can_msgobj_clear_fl(obj,TX_REQUEST);
- if (can_read_reg(chip, SJASR) & SR_TBS){
+ if (can_read_reg(chip, SJASR) & sjaSR_TBS){
obj->tx_retry_cnt=0;
sja1000p_irq_write_handler(chip, obj);
}
- clear_bit(OBJ_TX_LOCK,&obj->flags);
- if(!test_bit(OBJ_TX_REQUEST,&obj->flags)) break;
+ can_msgobj_clear_fl(obj,TX_LOCK);
+ if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
DEBUGMSG("TX looping in sja1000p_wakeup_tx\n");
}
- /* preempt_enable(); */
- can_spin_unlock(&dummy_lock);
+ can_preempt_enable();
return 0;
}
chipspecops->remote_request=sja1000p_remote_request;
chipspecops->enable_configuration=sja1000p_enable_configuration;
chipspecops->disable_configuration=sja1000p_disable_configuration;
+ chipspecops->attach_to_chip=sja1000p_attach_to_chip;
+ chipspecops->release_chip=sja1000p_release_chip;
chipspecops->set_btregs=sja1000p_set_btregs;
chipspecops->start_chip=sja1000p_start_chip;
chipspecops->stop_chip=sja1000p_stop_chip;
chipspecops->irq_handler=sja1000p_irq_handler;
+ chipspecops->irq_accept=NULL;
+ return 0;
+}
+
+/**
+ * sja1000p_fill_chipspecops - fills chip specific operations
+ * @chip: pointer to chip representation structure
+ *
+ * The function fills chip specific operations for sja1000 (PeliCAN) chip.
+ *
+ * Return Value: returns negative number in the case of fail
+ */
+int sja1000p_fill_chipspecops(struct canchip_t *chip)
+{
+ chip->chip_type="sja1000p";
+ chip->max_objects=1;
+ sja1000p_register(chip->chipspecops);
return 0;
}