]> rtime.felk.cvut.cz Git - lincan.git/blobdiff - lincan/src/sja1000.c
Structured comments updated.
[lincan.git] / lincan / src / sja1000.c
index 0955c76c6ceea53a8124a26f9e9267a25dbc375e..79ae13952f9b0fb05b0c5ff25673f7126f1a9f35 100644 (file)
@@ -1,31 +1,26 @@
 /* sja1000.c
  * Linux CAN-bus device driver.
  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
 /* sja1000.c
  * Linux CAN-bus device driver.
  * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
+ * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
+ * email:pisa@cmp.felk.cvut.cz
  * This software is released under the GPL-License.
  * This software is released under the GPL-License.
- * Version 0.6 18 Sept 2000
+ * Version lincan-0.2  9 Jul 2003
  */
 
  */
 
-#include <linux/autoconf.h>
-#if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
-#define MODVERSIONS
-#endif
-
-#if defined (MODVERSIONS)
-#include <linux/modversions.h>
-#endif
-
-#include <linux/delay.h>
-#include <asm/irq.h>
-
+#include "../include/can.h"
+#include "../include/can_sysdep.h"
 #include "../include/main.h"
 #include "../include/sja1000.h"
 
 #include "../include/main.h"
 #include "../include/sja1000.h"
 
+void sja1000_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj);
+void sja1000_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj);
+
 int sja1000_enable_configuration(struct chip_t *chip)
 {
        int i=0;
        unsigned flags;
 
 int sja1000_enable_configuration(struct chip_t *chip)
 {
        int i=0;
        unsigned flags;
 
-       disable_irq(chip->chip_irq);
+       can_disable_irq(chip->chip_irq);
 
        flags=can_read_reg(chip,SJACR);
 
 
        flags=can_read_reg(chip,SJACR);
 
@@ -37,7 +32,7 @@ int sja1000_enable_configuration(struct chip_t *chip)
        }
        if (i>=10) {
                CANMSG("Reset error\n");
        }
        if (i>=10) {
                CANMSG("Reset error\n");
-               enable_irq(chip->chip_irq);
+               can_enable_irq(chip->chip_irq);
                return -ENODEV;
        }
 
                return -ENODEV;
        }
 
@@ -62,7 +57,7 @@ int sja1000_disable_configuration(struct chip_t *chip)
                return -ENODEV;
        }
 
                return -ENODEV;
        }
 
-       enable_irq(chip->chip_irq);
+       can_enable_irq(chip->chip_irq);
 
        return 0;
 }
 
        return 0;
 }
@@ -80,9 +75,9 @@ int sja1000_chip_config(struct chip_t *chip)
        if (sja1000_standard_mask(chip,0x0000, 0xffff))
                return -ENODEV;
        
        if (sja1000_standard_mask(chip,0x0000, 0xffff))
                return -ENODEV;
        
-       if (!baudrate)
-               baudrate=1000;
-       if (sja1000_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
+       if (!chip->baudrate)
+               chip->baudrate=1000000;
+       if (sja1000_baud_rate(chip,chip->baudrate,chip->clock,0,75,0))
                return -ENODEV;
 
        /* Enable hardware interrupts */
                return -ENODEV;
 
        /* Enable hardware interrupts */
@@ -194,52 +189,36 @@ int sja1000_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
 int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
 {
        int i;
 int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
 {
        int i;
-       struct canfifo_t *fifo = chip->msgobj[0]->fifo;
-       int id;
+       
        i=can_read_reg(chip,SJASR);
        
        if (!(i&SR_RBS)) {
 //Temp
        i=can_read_reg(chip,SJASR);
        
        if (!(i&SR_RBS)) {
 //Temp
-       for (i=0; i<0x20; i++)
-               CANMSG("0x%x is 0x%x\n",i,can_read_reg(chip,i));
-               return 0;
+               for (i=0; i<0x20; i++)
+                       CANMSG("0x%x is 0x%x\n",i,can_read_reg(chip,i));
+                       return 0;
        }
        sja1000_start_chip(chip);
 
        }
        sja1000_start_chip(chip);
 
-       can_write_reg(chip, 0, SJACR); // disable interrupts for a moment
-// TODO: this would be best sja1000_irq_read_handler(chip);
-// now just duplicate the code.
-       do {
-               id = can_read_reg(chip, SJARXID0) | (can_read_reg(chip, SJARXID1)<<8);
-               fifo->rx_writep->length = id & 0x0f;
-               fifo->rx_writep->flags = id&ID0_RTR ? MSG_RTR : 0;
-               fifo->rx_writep->timestamp = 0;
-               fifo->rx_writep->cob = 0;
-               fifo->rx_writep->id = id>>5;
+    // disable interrupts for a moment
+       can_write_reg(chip, 0, SJACR); 
 
 
-               for (i=0; i<fifo->rx_writep->length; i++)
-                       fifo->rx_writep->data[i]=can_read_reg(chip, SJARXDAT0 + i);
+       sja1000_irq_read_handler(chip, obj);
 
 
-               fifo->rx_writep++;
-               if (fifo->rx_writep >= fifo->buf_rx_entry + MAX_BUF_LENGTH)
-                       fifo->rx_writep = fifo->buf_rx_entry;
-
-               can_write_reg(chip, CMR_RRB, SJACMR);
-
-       } while (can_read_reg(chip, SJASR) & SR_RBS);
-
-// enable interrupts
+    // enable interrupts
        can_write_reg(chip, CR_OIE | CR_EIE | CR_TIE | CR_RIE, SJACR);
 
 
        return 1;
 }
 
        can_write_reg(chip, CR_OIE | CR_EIE | CR_TIE | CR_RIE, SJACR);
 
 
        return 1;
 }
 
-#define MAX_TRANSMIT_WAIT_LOOPS 200
+#define MAX_TRANSMIT_WAIT_LOOPS 10
+
 int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj, 
                                                        struct canmsg_t *msg)
 {
        int i=0, id=0;
 int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj, 
                                                        struct canmsg_t *msg)
 {
        int i=0, id=0;
+       int len;
 
        sja1000_start_chip(chip); //sja1000 goes automatically into reset mode on errors
 
 
        sja1000_start_chip(chip); //sja1000 goes automatically into reset mode on errors
 
@@ -254,7 +233,7 @@ int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
                can_write_reg(chip, CMR_AT, SJACMR);
                i=0;
                while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
                can_write_reg(chip, CMR_AT, SJACMR);
                i=0;
                while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
-                                               i++<MAX_TRANSMIT_WAIT_LOOPS) {
+                               i++<MAX_TRANSMIT_WAIT_LOOPS) {
                        udelay(i);
                }
                if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
                        udelay(i);
                }
                if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
@@ -263,12 +242,14 @@ int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
                }
        }
 
                }
        }
 
-       id = (msg->id<<5) | ((msg->flags&MSG_RTR)?ID0_RTR:0) | msg->length;
+       len = msg->length;
+       if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
+       id = (msg->id<<5) | ((msg->flags&MSG_RTR)?ID0_RTR:0) | len;
 
        can_write_reg(chip, id>>8, SJATXID1);
        can_write_reg(chip, id & 0xff , SJATXID0);
 
 
        can_write_reg(chip, id>>8, SJATXID1);
        can_write_reg(chip, id & 0xff , SJATXID0);
 
-       for (i=0; i<msg->length; i++)
+       for (i=0; i<len; i++)
                can_write_reg(chip, msg->data[i], SJATXDAT0+i);
 
        return 0;
                can_write_reg(chip, msg->data[i], SJATXDAT0+i);
 
        return 0;
@@ -349,6 +330,144 @@ int sja1000_config_irqs(struct chip_t *chip, short irqs)
        return -ENOSYS;
 }
 
        return -ENOSYS;
 }
 
+
+can_irqreturn_t sja1000_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+{
+       unsigned irq_register;
+       struct chip_t *chip=(struct chip_t *)dev_id;
+       struct msgobj_t *obj=chip->msgobj[0];
+
+       irq_register=can_read_reg(chip, SJAIR);
+//     DEBUGMSG("sja1000_irq_handler: SJAIR:%02x\n",irq_register);
+//     DEBUGMSG("sja1000_irq_handler: SJASR:%02x\n",
+//                                     can_read_reg(chip, SJASR));
+
+       if ((irq_register & (IR_WUI|IR_DOI|IR_EI|IR_TI|IR_RI)) == 0)
+               return CAN_IRQ_NONE;
+
+       if ((irq_register & IR_RI) != 0) 
+               sja1000_irq_read_handler(chip, obj);
+
+       if ((irq_register & IR_TI) != 0) { 
+               can_msgobj_set_fl(obj,TX_REQUEST);
+               while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
+                       can_msgobj_clear_fl(obj,TX_REQUEST);
+
+                       if (can_read_reg(chip, SJASR) & SR_TBS)
+                               sja1000_irq_write_handler(chip, obj);
+
+                       can_msgobj_clear_fl(obj,TX_LOCK);
+                       if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
+               }
+       }
+
+       if ((irq_register & (IR_EI|IR_DOI)) != 0) { 
+               // Some error happened
+// FIXME: chip should be brought to usable state. Transmission cancelled if in progress.
+// Reset flag set to 0 if chip is already off the bus. Full state report
+               CANMSG("Error: status register: 0x%x irq_register: 0x%02x\n",
+                       can_read_reg(chip, SJASR), irq_register);
+               obj->ret=-1;
+
+               if(obj->tx_slot){
+                       canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_BUS);
+                       /*canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
+                       obj->tx_slot=NULL;*/
+               }
+       }
+
+       return CAN_IRQ_HANDLED;
+}
+
+void sja1000_irq_read_handler(struct chip_t *chip, struct msgobj_t *obj)
+{
+       int i=0, id=0, len;
+
+       do {
+               id = can_read_reg(chip, SJARXID0) | (can_read_reg(chip, SJARXID1)<<8);
+               obj->rx_msg.length = len = id & 0x0f;
+               obj->rx_msg.flags = id&ID0_RTR ? MSG_RTR : 0;
+               #ifdef CAN_MSG_VERSION_2
+               obj->rx_msg.timestamp.tv_sec = 0;
+               obj->rx_msg.timestamp.tv_usec = 0;
+               #else /* CAN_MSG_VERSION_2 */
+               obj->rx_msg.timestamp = 0;
+               #endif /* CAN_MSG_VERSION_2 */
+               obj->rx_msg.cob = 0;
+               obj->rx_msg.id = id>>5;
+
+               if(len > CAN_MSG_LENGTH) len = CAN_MSG_LENGTH;
+               for (i=0; i<len; i++)
+                       obj->rx_msg.data[i]=can_read_reg(chip, SJARXDAT0 + i);
+
+               can_write_reg(chip, CMR_RRB, SJACMR);
+
+               canque_filter_msg2edges(obj->qends, &obj->rx_msg);
+       } while(can_read_reg(chip, SJASR) & SR_RBS);
+}
+
+void sja1000_irq_write_handler(struct chip_t *chip, struct msgobj_t *obj)
+{
+       int cmd;
+       
+       if(obj->tx_slot){
+               /* Do local transmitted message distribution if enabled */
+               if (processlocal){
+                       obj->tx_slot->msg.flags |= MSG_LOCAL;
+                       canque_filter_msg2edges(obj->qends, &obj->tx_slot->msg);
+               }
+               /* Free transmitted slot */
+               canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
+               obj->tx_slot=NULL;
+       }
+
+       cmd=canque_test_outslot(obj->qends, &obj->tx_qedge, &obj->tx_slot);
+       if(cmd<0)
+               return;
+
+       if (chip->chipspecops->pre_write_config(chip, obj, &obj->tx_slot->msg)) {
+               obj->ret = -1;
+               canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_PREP);
+               canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
+               obj->tx_slot=NULL;
+               return;
+       }
+       if (chip->chipspecops->send_msg(chip, obj, &obj->tx_slot->msg)) {
+               obj->ret = -1;
+               canque_notify_inends(obj->tx_qedge, CANQUEUE_NOTIFY_ERRTX_SEND);
+               canque_free_outslot(obj->qends, obj->tx_qedge, obj->tx_slot);
+               obj->tx_slot=NULL;
+               return;
+       }
+}
+
+/**
+ * sja1000_wakeup_tx: - wakeups TX processing
+ * @chip: pointer to chip state structure
+ * @obj: pointer to message object structure
+ *
+ * Return Value: negative value reports error.
+ * File: src/sja1000.c
+ */
+int sja1000_wakeup_tx(struct chip_t *chip, struct msgobj_t *obj)
+{
+       can_preempt_disable();
+       
+       can_msgobj_set_fl(obj,TX_REQUEST);
+       while(!can_msgobj_test_and_set_fl(obj,TX_LOCK)){
+               can_msgobj_clear_fl(obj,TX_REQUEST);
+
+               if (can_read_reg(chip, SJASR) & SR_TBS)
+                       sja1000_irq_write_handler(chip, obj);
+       
+               can_msgobj_clear_fl(obj,TX_LOCK);
+               if(!can_msgobj_test_fl(obj,TX_REQUEST)) break;
+       }
+
+       can_preempt_enable();
+       return 0;
+}
+
 int sja1000_register(struct chipspecops_t *chipspecops)
 {
        chipspecops->chip_config = sja1000_chip_config;
 int sja1000_register(struct chipspecops_t *chipspecops)
 {
        chipspecops->chip_config = sja1000_chip_config;
@@ -362,6 +481,7 @@ int sja1000_register(struct chipspecops_t *chipspecops)
        chipspecops->pre_write_config = sja1000_pre_write_config;
        chipspecops->send_msg = sja1000_send_msg;
        chipspecops->check_tx_stat = sja1000_check_tx_stat;
        chipspecops->pre_write_config = sja1000_pre_write_config;
        chipspecops->send_msg = sja1000_send_msg;
        chipspecops->check_tx_stat = sja1000_check_tx_stat;
+       chipspecops->wakeup_tx=sja1000_wakeup_tx;
        chipspecops->remote_request = sja1000_remote_request;
        chipspecops->enable_configuration = sja1000_enable_configuration;
        chipspecops->disable_configuration = sja1000_disable_configuration;
        chipspecops->remote_request = sja1000_remote_request;
        chipspecops->enable_configuration = sja1000_enable_configuration;
        chipspecops->disable_configuration = sja1000_disable_configuration;