DEBUGMSG("Resetting %s hardware ...\n", candev->hwname);
while (i < 1000000) {
i++;
- outb(0x01, candev->res_addr);
+ can_outb(0x01, candev->res_addr);
}
- outb(0x0, candev->res_addr);
+ can_outb(0x0, candev->res_addr);
/* Check hardware reset status */
i = 0;
- while ((inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
+ while ((can_inb(candev->io_addr + iCPU) & iCPU_RST) && (i <= 15)) {
udelay(20000);
i++;
}
int pip_init_chip_data(struct candevice_t *candev, int chipnr)
{
i82527_fill_chipspecops(candev->chip[chipnr]);
- candev->chip[chipnr]->chip_base_addr = candev->io_addr;
+ candev->chip[chipnr]->chip_base_addr = can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 8000000;
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
unsigned char can_addr = 0, can_reg = 0;
DEBUGMSG("pip_program_irq\n");
/* Reset can controller */
- outb(0x01, candev->res_addr);
+ can_outb(0x01, candev->res_addr);
if (strcmp(candev->hwname, "pip5") == 0) {
irq_mask = PIP5_IRQ_MAP;
} else if (strcmp(candev->hwname, "pip6") == 0) {
return -ENODEV;
}
}
- can_reg = inb(PIP_CANRES_REG);
+ can_reg = can_inb(PIP_CANRES_REG);
DEBUGMSG("PIP_CANRES was 0x%x\n", can_reg);
can_reg = (candev->chip[0]->chip_irq << 4) | can_addr;
DEBUGMSG("Setting PIP_CANRES_REG to 0x%x\n", can_reg);
- outb((candev->chip[0]->chip_irq << 4) | can_addr, PIP_CANRES_REG);
+ can_outb((candev->chip[0]->chip_irq << 4) | can_addr, PIP_CANRES_REG);
/* re-enable the chip */
- outb(0x00, candev->res_addr);
+ can_outb(0x00, candev->res_addr);
return 0;
}
-void pip_write_register(unsigned data, unsigned long address)
+void pip_write_register(unsigned data, can_ioptr_t address)
{
- outb(data, address);
+ can_outb(data, address);
}
-unsigned pip_read_register(unsigned long address)
+unsigned pip_read_register(can_ioptr_t address)
{
- return inb(address);
+ return can_inb(address);
}
/* !!! Don't change these functions !!! */