--- /dev/null
+/* sja1000.c
+ * Linux CAN-bus device driver.
+ * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
+ * This software is released under the GPL-License.
+ * Version 0.6 18 Sept 2000
+ */
+
+#include <linux/autoconf.h>
+#if defined (CONFIG_MODVERSIONS) && !defined (MODVERSIONS)
+#define MODVERSIONS
+#endif
+
+#if defined (MODVERSIONS)
+#include <linux/modversions.h>
+#endif
+
+#include <linux/delay.h>
+#include <asm/irq.h>
+
+#include "../include/main.h"
+#include "../include/sja1000.h"
+
+int sja1000_enable_configuration(struct chip_t *chip)
+{
+ int i=0;
+ unsigned flags;
+
+ disable_irq(chip->chip_irq);
+
+ flags=can_read_reg(chip,SJACR);
+
+ while ((!(flags & CR_RR)) && (i<=10)) {
+ can_write_reg(chip,flags|CR_RR,SJACR);
+ udelay(100);
+ i++;
+ flags=can_read_reg(chip,SJACR);
+ }
+ if (i>=10) {
+ CANMSG("Reset error\n");
+ enable_irq(chip->chip_irq);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+int sja1000_disable_configuration(struct chip_t *chip)
+{
+ int i=0;
+ unsigned flags;
+
+ flags=can_read_reg(chip,SJACR);
+
+ while ( (flags & CR_RR) && (i<=10) ) {
+ can_write_reg(chip,flags & (CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
+ udelay(100);
+ i++;
+ flags=can_read_reg(chip,SJACR);
+ }
+ if (i>=10) {
+ CANMSG("Error leaving reset status\n");
+ return -ENODEV;
+ }
+
+ enable_irq(chip->chip_irq);
+
+ return 0;
+}
+
+int sja1000_chip_config(struct chip_t *chip)
+{
+ if (sja1000_enable_configuration(chip))
+ return -ENODEV;
+
+ /* Set mode, clock out, comparator */
+ can_write_reg(chip,chip->sja_cdr_reg,SJACDR);
+ /* Set driver output configuration */
+ can_write_reg(chip,chip->sja_ocr_reg,SJAOCR);
+
+ if (sja1000_standard_mask(chip,0x0000, 0xffff))
+ return -ENODEV;
+
+ if (!baudrate)
+ baudrate=1000;
+ if (sja1000_baud_rate(chip,1000*baudrate,chip->clock,0,75,0))
+ return -ENODEV;
+
+ /* Enable hardware interrupts */
+ can_write_reg(chip,(CR_RIE|CR_TIE|CR_EIE|CR_OIE),SJACR);
+
+ sja1000_disable_configuration(chip);
+
+ return 0;
+}
+
+int sja1000_standard_mask(struct chip_t *chip, unsigned short code, unsigned short mask)
+{
+ unsigned char write_code, write_mask;
+
+ if (sja1000_enable_configuration(chip))
+ return -ENODEV;
+
+ /* The acceptance code bits (SJAACR bits 0-7) and the eight most
+ * significant bits of the message identifier (id.10 to id.3) must be
+ * equal to those bit positions which are marked relevant by the
+ * acceptance mask bits (SJAAMR bits 0-7).
+ * (id.10 to id.3) = (SJAACR.7 to SJAACR.0) v (SJAAMR.7 to SJAAMR.0)
+ * (Taken from Philips sja1000 Data Sheet)
+ */
+ write_code = (unsigned char) code >> 3;
+ write_mask = (unsigned char) mask >> 3;
+
+ can_write_reg(chip,write_code,SJAACR);
+ can_write_reg(chip,write_mask,SJAAMR);
+
+ DEBUGMSG("Setting acceptance code to 0x%lx\n",(unsigned long)code);
+ DEBUGMSG("Setting acceptance mask to 0x%lx\n",(unsigned long)mask);
+
+ sja1000_disable_configuration(chip);
+
+ return 0;
+}
+
+/* Set communication parameters.
+ * param rate baud rate in Hz
+ * param clock frequency of sja1000 clock in Hz (ISA osc is 14318000)
+ * param sjw synchronization jump width (0-3) prescaled clock cycles
+ * param sampl_pt sample point in % (0-100) sets (TSEG1+2)/(TSEG1+TSEG2+3) ratio
+ * param flags fields BTR1_SAM, OCMODE, OCPOL, OCTP, OCTN, CLK_OFF, CBP
+ */
+int sja1000_baud_rate(struct chip_t *chip, int rate, int clock, int sjw,
+ int sampl_pt, int flags)
+{
+ int best_error = 1000000000, error;
+ int best_tseg=0, best_brp=0, best_rate=0, brp=0;
+ int tseg=0, tseg1=0, tseg2=0;
+
+ if (sja1000_enable_configuration(chip))
+ return -ENODEV;
+
+ clock /=2;
+
+ /* tseg even = round down, odd = round up */
+ for (tseg=(0+0+2)*2; tseg<=(MAX_TSEG2+MAX_TSEG1+2)*2+1; tseg++) {
+ brp = clock/((1+tseg/2)*rate)+tseg%2;
+ if (brp == 0 || brp > 64)
+ continue;
+ error = rate - clock/(brp*(1+tseg/2));
+ if (error < 0)
+ error = -error;
+ if (error <= best_error) {
+ best_error = error;
+ best_tseg = tseg/2;
+ best_brp = brp-1;
+ best_rate = clock/(brp*(1+tseg/2));
+ }
+ }
+ if (best_error && (rate/best_error < 10)) {
+ CANMSG("baud rate %d is not possible with %d Hz clock\n",
+ rate, 2*clock);
+ CANMSG("%d bps. brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d\n",
+ best_rate, best_brp, best_tseg, tseg1, tseg2);
+ return -EINVAL;
+ }
+ tseg2 = best_tseg-(sampl_pt*(best_tseg+1))/100;
+ if (tseg2 < 0)
+ tseg2 = 0;
+ if (tseg2 > MAX_TSEG2)
+ tseg2 = MAX_TSEG2;
+ tseg1 = best_tseg-tseg2-2;
+ if (tseg1 > MAX_TSEG1) {
+ tseg1 = MAX_TSEG1;
+ tseg2 = best_tseg-tseg1-2;
+ }
+
+ DEBUGMSG("Setting %d bps.\n", best_rate);
+ DEBUGMSG("brp=%d, best_tseg=%d, tseg1=%d, tseg2=%d, sampl_pt=%d\n",
+ best_brp, best_tseg, tseg1, tseg2,
+ (100*(best_tseg-tseg2)/(best_tseg+1)));
+
+
+ can_write_reg(chip, sjw<<6 | best_brp, SJABTR0);
+ can_write_reg(chip, ((flags & BTR1_SAM) != 0)<<7 | tseg2<<4 | tseg1,
+ SJABTR1);
+// can_write_reg(chip, OCR_MODE_NORMAL | OCR_TX0_LH | OCR_TX1_ZZ, SJAOCR);
+ /* BASIC mode, bypass input comparator */
+// can_write_reg(chip, CDR_CBP| /* CDR_CLK_OFF | */ 7, SJACDR);
+
+ sja1000_disable_configuration(chip);
+
+ return 0;
+}
+
+int sja1000_pre_read_config(struct chip_t *chip, struct msgobj_t *obj)
+{
+ int i;
+ struct canfifo_t *fifo = chip->msgobj[0]->fifo;
+ int id;
+ i=can_read_reg(chip,SJASR);
+
+ if (!(i&SR_RBS)) {
+//Temp
+ for (i=0; i<0x20; i++)
+ CANMSG("0x%x is 0x%x\n",i,can_read_reg(chip,i));
+ return 0;
+ }
+ sja1000_start_chip(chip);
+
+ can_write_reg(chip, 0, SJACR); // disable interrupts for a moment
+// TODO: this would be best sja1000_irq_read_handler(chip);
+// now just duplicate the code.
+ do {
+ id=(can_read_reg(chip, SJARXID1)<<8) + can_read_reg(chip,
+ SJARXID0);
+ fifo->buf_rx_entry[fifo->head].length = (id>>8) & 0x0f;
+ fifo->buf_rx_entry[fifo->head].id = id>>5;
+ fifo->buf_rx_entry[fifo->head].flags = id&ID0_RTR ?
+ MSG_RTR : 0;
+ fifo->buf_rx_entry[fifo->head].timestamp = 0;
+ fifo->buf_rx_entry[fifo->head].cob = 0;
+ for (i=0; i<fifo->buf_rx_entry[fifo->head].length; i++) {
+ fifo->buf_rx_entry[fifo->head].data[i] =
+ can_read_reg(chip,SJARXDAT0 + i);
+ }
+ fifo->head++;
+ if (fifo->head == MAX_BUF_LENGTH -1)
+ fifo->head = 0;
+ can_write_reg(chip, CMR_RRB, SJACMR);
+ } while (can_read_reg(chip, SJASR) & SR_RBS);
+
+// enable interrupts
+ can_write_reg(chip, CR_OIE | CR_EIE | CR_TIE | CR_RIE, SJACR);
+
+
+ return 1;
+}
+
+#define MAX_TRANSMIT_WAIT_LOOPS 200
+int sja1000_pre_write_config(struct chip_t *chip, struct msgobj_t *obj,
+ struct canmsg_t *msg)
+{
+ int i=0, id=0;
+
+ sja1000_start_chip(chip); //sja1000 goes automatically into reset mode on errors
+
+ /* Wait until Transmit Buffer Status is released */
+ while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
+ i++<MAX_TRANSMIT_WAIT_LOOPS) {
+ udelay(i);
+ }
+
+ if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
+ CANMSG("Transmit timed out, cancelling\n");
+ can_write_reg(chip, CMR_AT, SJACMR);
+ i=0;
+ while ( !(can_read_reg(chip, SJASR) & SR_TBS) &&
+ i++<MAX_TRANSMIT_WAIT_LOOPS) {
+ udelay(i);
+ }
+ if (!(can_read_reg(chip, SJASR) & SR_TBS)) {
+ CANMSG("Could not cancel, please reset\n");
+ return -EIO;
+ }
+ }
+
+ id = (msg->id<<5) | ((msg->flags&MSG_RTR)?ID0_RTR:0) | msg->length;
+
+ can_write_reg(chip, id>>8, SJATXID1);
+ can_write_reg(chip, id & 0xff , SJATXID0);
+
+ for (i=0; i<msg->length; i++)
+ can_write_reg(chip, msg->data[i], SJATXDAT0+i);
+
+ return 0;
+}
+
+int sja1000_send_msg(struct chip_t *chip, struct msgobj_t *obj,
+ struct canmsg_t *msg)
+{
+ can_write_reg(chip, CMR_TR, SJACMR);
+
+ return 0;
+}
+
+int sja1000_check_tx_stat(struct chip_t *chip)
+{
+ if (can_read_reg(chip,SJASR) & SR_TCS)
+ return 0;
+ else
+ return 1;
+}
+
+int sja1000_set_btregs(struct chip_t *chip, unsigned short btr0,
+ unsigned short btr1)
+{
+ if (sja1000_enable_configuration(chip))
+ return -ENODEV;
+
+ can_write_reg(chip, btr0, SJABTR0);
+ can_write_reg(chip, btr1, SJABTR1);
+
+ sja1000_disable_configuration(chip);
+
+ return 0;
+}
+
+int sja1000_start_chip(struct chip_t *chip)
+{
+ unsigned short flags = 0;
+
+ flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
+ can_write_reg(chip, flags, SJACR);
+
+ return 0;
+}
+
+int sja1000_stop_chip(struct chip_t *chip)
+{
+ unsigned short flags = 0;
+
+ flags = can_read_reg(chip, SJACR) & (CR_RIE|CR_TIE|CR_EIE|CR_OIE);
+ can_write_reg(chip, flags|CR_RR, SJACR);
+
+ return 0;
+}
+
+int sja1000_remote_request(struct chip_t *chip, struct msgobj_t *obj)
+{
+ CANMSG("sja1000_remote_request not implemented\n");
+ return -ENOSYS;
+}
+
+int sja1000_extended_mask(struct chip_t *chip, unsigned long code,
+ unsigned long mask)
+{
+ CANMSG("sja1000_extended_mask not implemented\n");
+ return -ENOSYS;
+}
+
+int sja1000_clear_objects(struct chip_t *chip)
+{
+ CANMSG("sja1000_clear_objects not implemented\n");
+ return -ENOSYS;
+}
+
+int sja1000_config_irqs(struct chip_t *chip, short irqs)
+{
+ CANMSG("sja1000_config_irqs not implemented\n");
+ return -ENOSYS;
+}
+
+int sja1000_register(struct chipspecops_t *chipspecops)
+{
+ chipspecops->chip_config = sja1000_chip_config;
+ chipspecops->baud_rate = sja1000_baud_rate;
+ chipspecops->standard_mask = sja1000_standard_mask;
+ chipspecops->extended_mask = sja1000_extended_mask;
+ chipspecops->message15_mask = sja1000_extended_mask;
+ chipspecops->clear_objects = sja1000_clear_objects;
+ chipspecops->config_irqs = sja1000_config_irqs;
+ chipspecops->pre_read_config = sja1000_pre_read_config;
+ chipspecops->pre_write_config = sja1000_pre_write_config;
+ chipspecops->send_msg = sja1000_send_msg;
+ chipspecops->check_tx_stat = sja1000_check_tx_stat;
+ chipspecops->remote_request = sja1000_remote_request;
+ chipspecops->enable_configuration = sja1000_enable_configuration;
+ chipspecops->disable_configuration = sja1000_disable_configuration;
+ chipspecops->set_btregs = sja1000_set_btregs;
+ chipspecops->start_chip = sja1000_start_chip;
+ chipspecops->stop_chip = sja1000_stop_chip;
+ chipspecops->irq_handler = sja1000_irq_handler;
+ return 0;
+}
projects / lincan.git / blobdiff