-// int i=0;
-
-// DEBUGMSG("Resetting pcm3680 hardware ...\n");
-// pcm3680_write_register(0x01, candevices_p[card]->io_addr +
-// 0x100); // Write arbitrary data to reset mem
-// pcm3680_write_register(0x01, candevices_p[card]->io_addr +
-// 0x300); // Write arbitrary data to reset mem
-// udelay(20000);
-
-// pcm3680_write_register(0x00, candevices_p[card]->io_addr + SJACR);
-// pcm3680_write_register(0x00, candevices_p[card]->io_addr + SJACR+0x200);
-
- /* Check hardware reset status chip 0 */
-/* i=0;
- while ( (pcm3680_read_register(candevices_p[card]->io_addr + SJACR)
- & CR_RR) && (i<=15) ) {
- udelay(20000);
- i++;
- }
- if (i>=15) {
- CANMSG("Reset status timeout!\n");
- CANMSG("Please check your hardware.\n");
- return -ENODEV;
- }
- else
- DEBUGMSG("Chip[0] reset status ok.\n");
-*/
- /* Check hardware reset status chip 1 */
-/* i=0;
- while ( (pcm3680_read_register( candevices_p[card]->io_addr + SJACR +
- 0x200) & CR_RR) && (i<=15) ) {
- udelay(20000);
- i++;
- }
- if (i>=15) {
- CANMSG("Reset status timeout!\n");
- CANMSG("Please check your hardware.\n");
- return -ENODEV;
+ int i=0;
+ struct chip_t *chip;
+ int chipnr;
+
+ DEBUGMSG("Resetting pcm3680 hardware ...\n");
+ for(chipnr=0;chipnr<candev->nr_sja1000_chips;chipnr++) {
+ chip=candev->chip[chipnr];
+ pcm3680_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+ udelay(1000);
+ pcm3680_write_register(0x00, chip->chip_base_addr + SJAIER);
+ /* Write arbitrary data to reset chip */
+ pcm3680_write_register(0x01, chip->chip_base_addr + 0x100);
+ udelay(1000);
+ i=20;
+ while (pcm3680_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+ if(!i--) return -ENODEV;
+ udelay(1000);
+ pcm3680_write_register(0, chip->chip_base_addr+SJAMOD);
+ }
+ udelay(1000);
+ pcm3680_write_register(CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ pcm3680_write_register(0x00, chip->chip_base_addr + SJAIER);