# define EMS_CPCPCI_PCICAN_VENDOR 0x110a
# define EMS_CPCPCI_PCICAN_ID 0x2104
+/*The PSB4610 is used as PCI to local bus bridge*/
+/*BAR0 - MEM - bridge control registers*/
+
+/*BAR1 - MEM - parallel interface*/
+/* 0 more EMS control registers
+ * 0x400 the first SJA1000
+ * 0x600 the second SJA1000
+ * each register occupies 4 bytes
+ */
+
/*AMCC 5920*/
#define S5920_OMB 0x0C
#define S5920_IMB 0x1C
}
-void ems_cpcpci_write_register(unsigned char data, unsigned long address)
+void ems_cpcpci_write_register(unsigned data, unsigned long address)
{
address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
*(EMS_CPCPCI_BYTES_PER_REG-1));
- readb(data,address);
+ writeb(data,address);
}
unsigned ems_cpcpci_read_register(unsigned long address)
{
address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
*(EMS_CPCPCI_BYTES_PER_REG-1));
- return inb(address);
+ return readb(address);
}
int ems_cpcpci_reset(struct candevice_t *candev)
if(!candev->chip[chip_nr]) continue;
chip=candev->chip[chip_nr];
- ems_cpcpci_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+ ems_cpcpci_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
udelay(1000);
cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
- ems_cpcpci_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
i=20;
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
- while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+ while (ems_cpcpci_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
if(!i--) return -ENODEV;
udelay(1000);
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAMOD);
}
cdr=ems_cpcpci_read_register(chip->chip_base_addr+SJACDR);
- ems_cpcpci_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
candev->chip[chipnr]->sja_ocr_reg = EMS_CPCPCI_OCR_DEFAULT_STD;
candev->chip[chipnr]->clock = 8000000;
candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;