-/* pcccan.c
- * Linux CAN-bus device driver.
- * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
- * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
- * email:pisa@cmp.felk.cvut.cz
- * This software is released under the GPL-License.
- * Version lincan-0.2 9 Jul 2003
- */
+/**************************************************************************/
+/* File: pcccan.c - PCCCAN board support */
+/* */
+/* LinCAN - (Not only) Linux CAN bus driver */
+/* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
+/* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
+/* Funded by OCERA and FRESCOR IST projects */
+/* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
+/* */
+/* LinCAN is free software; you can redistribute it and/or modify it */
+/* under terms of the GNU General Public License as published by the */
+/* Free Software Foundation; either version 2, or (at your option) any */
+/* later version. LinCAN is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
+/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
+/* General Public License for more details. You should have received a */
+/* copy of the GNU General Public License along with LinCAN; see file */
+/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
+/* Cambridge, MA 02139, USA. */
+/* */
+/* To allow use of LinCAN in the compact embedded systems firmware */
+/* and RT-executives (RTEMS for example), main authors agree with next */
+/* special exception: */
+/* */
+/* Including LinCAN header files in a file, instantiating LinCAN generics */
+/* or templates, or linking other files with LinCAN objects to produce */
+/* an application image/executable, does not by itself cause the */
+/* resulting application image/executable to be covered by */
+/* the GNU General Public License. */
+/* This exception does not however invalidate any other reasons */
+/* why the executable file might be covered by the GNU Public License. */
+/* Publication of enhanced or derived LinCAN files is required although. */
+/**************************************************************************/
/* This file contains the low level functions for the pcccan-1 card from Gespac.
* You can probably find more information at http://www.gespac.com
*/
-#include <linux/autoconf.h>
-
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <linux/sched.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-
+#include "../include/can.h"
+#include "../include/can_sysdep.h"
#include "../include/main.h"
#include "../include/pcccan.h"
#include "../include/i82527.h"
int pcccan_irq=-1;
unsigned long pcccan_base=0x0;
+static CAN_DEFINE_SPINLOCK(pcccan_port_lock);
+
/*
* IO_RANGE is the io-memory range that gets reserved, please adjust according
* your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
*
* The function pcccan_request_io() is used to reserve the io-memory. If your
* hardware uses a dedicated memory range as hardware control registers you
- * will have to add the code to reserve this memory as well.
+ * will have to add the code to reserve this memory as well.
* %IO_RANGE is the io-memory range that gets reserved, please adjust according
* your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
* #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
* pcccan_reset - hardware reset routine
* @candev: Pointer to candevice/board structure
*
- * The function pcccan_reset() is used to give a hardware reset. This is
- * rather hardware specific so I haven't included example code. Don't forget to
+ * The function pcccan_reset() is used to give a hardware reset. This is
+ * rather hardware specific so I haven't included example code. Don't forget to
* check the reset status of the chip before returning.
* Return Value: The function returns zero on success or %-ENODEV on failure
* File: src/pcccan.c
DEBUGMSG("Resetting pcccan-1 hardware ...\n");
while (i < 1000000) {
i++;
- outb(0x0,candev->res_addr);
+ can_outb(0x0,candev->res_addr);
}
/* Check hardware reset status */
i=0;
- outb(iCPU,candev->io_addr+0x1);
- while ( (inb(candev->io_addr+0x2)&0x80) && (i<=15) ) {
- udelay(20000);
+ can_outb(iCPU,candev->io_addr+0x1);
+ while ( (can_inb(candev->io_addr+0x2)&0x80) && (i<=15) ) {
+ mdelay(20);
i++;
}
if (i>=15) {
DEBUGMSG("Chip reset status ok.\n");
return 0;
-}
+}
#define NR_82527 1
#define NR_SJA1000 0
* %RESET_ADDR represents the io-address of the hardware reset register.
* %NR_82527 represents the number of intel 82527 chips on the board.
* %NR_SJA1000 represents the number of philips sja1000 chips on the board.
- * The flags entry can currently only be %PROGRAMMABLE_IRQ to indicate that
+ * The flags entry can currently only be %CANDEV_PROGRAMMABLE_IRQ to indicate that
* the hardware uses programmable interrupts.
* Return Value: The function always returns zero
* File: src/pcccan.c
*/
-int pcccan_init_hw_data(struct candevice_t *candev)
+int pcccan_init_hw_data(struct candevice_t *candev)
{
candev->res_addr=candev->io_addr;
candev->nr_82527_chips=NR_82527;
candev->nr_sja1000_chips=NR_SJA1000;
candev->nr_all_chips=NR_82527+NR_SJA1000;
- candev->flags &= ~PROGRAMMABLE_IRQ;
+ candev->flags &= ~CANDEV_PROGRAMMABLE_IRQ;
return 0;
}
-#define CHIP_TYPE "i82527"
/**
* pcccan_init_chip_data - Initialize chips
* @candev: Pointer to candevice/board structure
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
- * The entry @int_bus_reg holds hardware specific options for the Bus
+ * The entry @int_bus_reg holds hardware specific options for the Bus
* Configuration register. Options defined in the %i82527.h file:
* %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
* The entry @int_cpu_reg holds hardware specific options for the cpu interface
*/
int pcccan_init_chip_data(struct candevice_t *candev, int chipnr)
{
- candev->chip[chipnr]->chip_type=CHIP_TYPE;
- candev->chip[chipnr]->chip_base_addr=candev->io_addr;
+ i82527_fill_chipspecops(candev->chip[chipnr]);
+ candev->chip[chipnr]->chip_base_addr=can_ioport2ioptr(candev->io_addr);
candev->chip[chipnr]->clock = 16000000;
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC | iCPU_DMC;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1 | iCLK_CD0;
* CAN chip. In case of the sja1000 there's only one message object but on the
* i82527 chip there are 15.
* The code below is for a i82527 chip and initializes the object base addresses
- * The entry @obj_base_addr represents the first memory address of the message
+ * The entry @obj_base_addr represents the first memory address of the message
* object. In case of the sja1000 @obj_base_addr is taken the same as the chips
* base address.
* Unless the hardware uses a segmented memory map, flags can be set zero.
* Return Value: The function always returns zero
* File: src/pcccan.c
*/
-int pcccan_init_obj_data(struct chip_t *chip, int objnr)
+int pcccan_init_obj_data(struct canchip_t *chip, int objnr)
{
chip->msgobj[objnr]->obj_base_addr=(objnr+1)*0x10;
- chip->msgobj[objnr]->flags=0;
-
+
return 0;
}
* pcccan_program_irq - program interrupts
* @candev: Pointer to candevice/board structure
*
- * The function pcccan_program_irq() is used for hardware that uses
+ * The function pcccan_program_irq() is used for hardware that uses
* programmable interrupts. If your hardware doesn't use programmable interrupts
- * you should not set the @candevices_t->flags entry to %PROGRAMMABLE_IRQ and
- * leave this function unedited. Again this function is hardware specific so
+ * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
+ * leave this function unedited. Again this function is hardware specific so
* there's no example code.
* Return value: The function returns zero on success or %-ENODEV on failure
* File: src/pcccan.c
* Return Value: The function does not return a value
* File: src/pcccan.c
*/
-void pcccan_write_register(unsigned char data, unsigned long address)
+void pcccan_write_register(unsigned data, can_ioptr_t address)
{
- disable_irq(pcccan_irq);
- outb(address - pcccan_base, pcccan_base+1);
- outb(data, pcccan_base+6);
- enable_irq(pcccan_irq);
+ can_spin_irqflags_t flags;
+ can_spin_lock_irqsave(&pcccan_port_lock,flags);
+ can_outb(address - pcccan_base, pcccan_base+1);
+ can_outb(data, pcccan_base+6);
+ can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
}
/**
* Return Value: The function returns the value stored in @address
* File: src/pcccan.c
*/
-unsigned pcccan_read_register(unsigned long address)
+unsigned pcccan_read_register(can_ioptr_t address)
{
unsigned ret;
- disable_irq(pcccan_irq);
- outb(address - pcccan_base, pcccan_base+1);
- ret=inb(pcccan_base+2);
- enable_irq(pcccan_irq);
+ can_spin_irqflags_t flags;
+ can_spin_lock_irqsave(&pcccan_port_lock,flags);
+ can_outb(address - pcccan_base, pcccan_base+1);
+ ret=can_inb(pcccan_base+2);
+ can_spin_unlock_irqrestore(&pcccan_port_lock,flags);
return ret;
}
projects / lincan.git / blobdiff