* possible to load the driver with the hardware option hw=bfadcan.
*/
-#define __NO_VERSION__ /* this is not a main module, do not include module info */
-
-#include <linux/autoconf.h>
-
-#include <linux/module.h>
-
-#include <linux/version.h>
-#include <linux/ioport.h>
-#include <linux/delay.h>
-#include <asm/errno.h>
-#include <asm/io.h>
-
-#if (LINUX_VERSION_CODE <= KERNEL_VERSION(2,3,0))
-#include <asm/spinlock.h>
-#else
-#include <linux/spinlock.h>
-#endif
#define WINDOWED_ACCESS
+#include "../include/can.h"
+#include "../include/can_sysdep.h"
#include "../include/main.h"
#include "../include/i82527.h"
#include "../include/sja1000p.h"
+#define __NO_VERSION__
+#include <linux/module.h>
+
long clock_freq;
MODULE_PARM(clock_freq,"i");
/* cli and sti are not allowed in 2.5.5x SMP kernels */
#ifdef WINDOWED_ACCESS
-spinlock_t bfadcan_win_lock=SPIN_LOCK_UNLOCKED;
+static can_spinlock_t bfadcan_win_lock=SPIN_LOCK_UNLOCKED;
#endif
/*
#endif
unsigned bfadcan_read_register(unsigned long address);
-void bfadcan_write_register(unsigned char data, unsigned long address);
+void bfadcan_write_register(unsigned data, unsigned long address);
/**
struct chip_t *chip=candev->chip[0];
unsigned cdr;
- bfadcan_write_register(MOD_RM, chip->chip_base_addr+SJAMOD);
+ bfadcan_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
udelay(1000);
cdr=bfadcan_read_register(chip->chip_base_addr+SJACDR);
- bfadcan_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ bfadcan_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
bfadcan_write_register(0, chip->chip_base_addr+SJAIER);
i=20;
bfadcan_write_register(0, chip->chip_base_addr+SJAMOD);
- while (bfadcan_read_register(chip->chip_base_addr+SJAMOD)&MOD_RM){
+ while (bfadcan_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
if(!i--) return -ENODEV;
udelay(1000);
bfadcan_write_register(0, chip->chip_base_addr+SJAMOD);
}
cdr=bfadcan_read_register(chip->chip_base_addr+SJACDR);
- bfadcan_write_register(cdr|CDR_PELICAN, chip->chip_base_addr+SJACDR);
+ bfadcan_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
bfadcan_write_register(0, chip->chip_base_addr+SJAIER);
* %RESET_ADDR represents the io-address of the hardware reset register.
* %NR_82527 represents the number of intel 82527 chips on the board.
* %NR_SJA1000 represents the number of philips sja1000 chips on the board.
- * The flags entry can currently only be %PROGRAMMABLE_IRQ to indicate that
+ * The flags entry can currently only be %CANDEV_PROGRAMMABLE_IRQ to indicate that
* the hardware uses programmable interrupts.
* Return Value: The function always returns zero
* File: src/bfadcan.c
candev->nr_82527_chips=NR_82527;
candev->nr_sja1000_chips=NR_SJA1000;
candev->nr_all_chips=NR_82527+NR_SJA1000;
- candev->flags |= 0 /* PROGRAMMABLE_IRQ */ ;
+ candev->flags |= 0 /* CANDEV_PROGRAMMABLE_IRQ */ ;
return 0;
}
* The @clock entry holds the chip clock value in Hz.
* The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
* register. Options defined in the %sja1000.h file:
- * %CDR_CLKOUT_MASK, %CDR_CLK_OFF, %CDR_RXINPEN, %CDR_CBP, %CDR_PELICAN
+ * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
* The entry @sja_ocr_reg holds hardware specific options for the Output Control
* register. Options defined in the %sja1000.h file:
- * %OCR_MODE_BIPHASE, %OCR_MODE_TEST, %OCR_MODE_NORMAL, %OCR_MODE_CLOCK,
- * %OCR_TX0_LH, %OCR_TX1_ZZ.
+ * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
+ * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
* The entry @int_clk_reg holds hardware specific options for the Clock Out
* register. Options defined in the %i82527.h file:
* %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
candev->chip[chipnr]->int_cpu_reg = iCPU_DSC;
candev->chip[chipnr]->int_clk_reg = iCLK_SL1;
candev->chip[chipnr]->int_bus_reg = iBUS_CBY;
- candev->chip[chipnr]->sja_cdr_reg = CDR_CBP | CDR_CLK_OFF;
- candev->chip[chipnr]->sja_ocr_reg = OCR_MODE_NORMAL |
- OCR_TX0_LH;
+ candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
+ candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL |
+ sjaOCR_TX0_LH;
id1 = inb(0xe284);
id2 = inb(0xe285);
int bfadcan_init_obj_data(struct chip_t *chip, int objnr)
{
chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10;
- chip->msgobj[objnr]->flags=0;
return 0;
}
*
* The function bfadcan_program_irq() is used for hardware that uses
* programmable interrupts. If your hardware doesn't use programmable interrupts
- * you should not set the @candevices_t->flags entry to %PROGRAMMABLE_IRQ and
+ * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
* leave this function unedited. Again this function is hardware specific so
* there's no example code.
* Return value: The function returns zero on success or %-ENODEV on failure
* Return Value: The function does not return a value
* File: src/bfadcan.c
*/
-void bfadcan_write_register(unsigned char data, unsigned long address)
+void bfadcan_write_register(unsigned data, unsigned long address)
{
#ifdef WINDOWED_ACCESS
- long flags;
- spin_lock_irqsave(&bfadcan_win_lock,flags);
+ can_spin_irqflags_t flags;
+ can_spin_lock_irqsave(&bfadcan_win_lock,flags);
outb(address&0x00ff,0x200);
outb(data, 0x201);
- spin_unlock_irqrestore(&bfadcan_win_lock,flags);
+ can_spin_unlock_irqrestore(&bfadcan_win_lock,flags);
#else
outb(data,address);
#endif
unsigned bfadcan_read_register(unsigned long address)
{
#ifdef WINDOWED_ACCESS
- long flags;
+ can_spin_irqflags_t flags;
int ret;
- spin_lock_irqsave(&bfadcan_win_lock,flags);
+ can_spin_lock_irqsave(&bfadcan_win_lock,flags);
outb(address&0x00ff,0x200);
ret = inb(0x201);
- spin_unlock_irqrestore(&bfadcan_win_lock,flags);
+ can_spin_unlock_irqrestore(&bfadcan_win_lock,flags);
return ret;
#else
return inb(address);
projects / lincan.git / blobdiff