-/* ems_cpcpci.c - support for EMS-WUENSCHE CPC-PCI card
- * Linux CAN-bus device driver.
- * The card support added by Paolo Grisleri <grisleri@ce.unipr.it>
- * This software is released under the GPL-License.
- * Version lincan-0.3 17 Jun 2004
- */
+/**************************************************************************/
+/* File: ems_cpcpci.c - support for EMS-WUENSCHE CPC-PCI card */
+/* */
+/* LinCAN - (Not only) Linux CAN bus driver */
+/* Copyright (C) 2002-2009 DCE FEE CTU Prague <http://dce.felk.cvut.cz> */
+/* Copyright (C) 2002-2009 Pavel Pisa <pisa@cmp.felk.cvut.cz> */
+/* Copyright (C) 2004 Paolo Grisleri <grisleri@ce.unipr.it> */
+/* Funded by OCERA and FRESCOR IST projects */
+/* Based on CAN driver code by Arnaud Westenberg <arnaud@wanadoo.nl> */
+/* */
+/* LinCAN is free software; you can redistribute it and/or modify it */
+/* under terms of the GNU General Public License as published by the */
+/* Free Software Foundation; either version 2, or (at your option) any */
+/* later version. LinCAN is distributed in the hope that it will be */
+/* useful, but WITHOUT ANY WARRANTY; without even the implied warranty */
+/* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU */
+/* General Public License for more details. You should have received a */
+/* copy of the GNU General Public License along with LinCAN; see file */
+/* COPYING. If not, write to the Free Software Foundation, 675 Mass Ave, */
+/* Cambridge, MA 02139, USA. */
+/* */
+/* To allow use of LinCAN in the compact embedded systems firmware */
+/* and RT-executives (RTEMS for example), main authors agree with next */
+/* special exception: */
+/* */
+/* Including LinCAN header files in a file, instantiating LinCAN generics */
+/* or templates, or linking other files with LinCAN objects to produce */
+/* an application image/executable, does not by itself cause the */
+/* resulting application image/executable to be covered by */
+/* the GNU General Public License. */
+/* This exception does not however invalidate any other reasons */
+/* why the executable file might be covered by the GNU Public License. */
+/* Publication of enhanced or derived LinCAN files is required although. */
+/**************************************************************************/
#include "../include/can.h"
#include "../include/can_sysdep.h"
* each register occupies 4 bytes
*/
-/*PSB4610 PITA-2 bridge control registers*/
+/*PSB4610 PITA-2 bridge control registers*/
#define PITA2_ICR 0x00 /* Interrupt Control Register */
-#define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
-#define PITA2_ICR_INT0_En 0x00020000 /* [RW] Enable INT0 */
+#define PITA2_ICR_INT0 0x00000002 /* [RC] INT0 Active/Clear */
+#define PITA2_ICR_GP0_INT 0x00000004 /* [RC] GP0 Interrupt */
+ /* GP0_Int_En=1, GP0_Out_En=0 and low detected */
+#define PITA2_ICR_GP1_INT 0x00000008 /* [RC] GP1 Interrupt */
+#define PITA2_ICR_GP2_INT 0x00000010 /* [RC] GP2 Interrupt */
+#define PITA2_ICR_GP3_INT 0x00000020 /* [RC] GP2 Interrupt */
+#define PITA2_ICR_INT0_En 0x00020000 /* [RW] Enable INT0 */
#define PITA2_MISC 0x1C /* Miscellaneous Register */
#define PITA2_MISC_CONFIG 0x04000000
/*
-The board configuration is probably following:
-" RX1 is connected to ground.
-" TX1 is not connected.
-" CLKO is not connected.
-" Setting the OCR register to 0xDA is a good idea.
- This means normal output mode , push-pull and the correct polarity.
-" In the CDR register, you should set CBP to 1.
+The board configuration is probably following:
+" RX1 is connected to ground.
+" TX1 is not connected.
+" CLKO is not connected.
+" Setting the OCR register to 0xDA is a good idea.
+ This means normal output mode , push-pull and the correct polarity.
+" In the CDR register, you should set CBP to 1.
You will probably also want to set the clock divider value to 7
- (meaning direct oscillator output) because the second SJA1000 chip
+ (meaning direct oscillator output) because the second SJA1000 chip
is driven by the first one CLKOUT output.
*/
void ems_cpcpci_disconnect_irq(struct candevice_t *candev)
{
/* Disable interrupts from card */
- writel(0, candev->dev_base_addr + PITA2_ICR);
+ can_writel(0, candev->aux_base_addr + PITA2_ICR);
}
void ems_cpcpci_connect_irq(struct candevice_t *candev)
{
/* Enable interrupts from card */
- writel(PITA2_ICR_INT0_En, candev->dev_base_addr + PITA2_ICR);
+ can_writel(PITA2_ICR_INT0_En, candev->aux_base_addr + PITA2_ICR);
}
#endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
pita2_addr=pci_resource_start(candev->sysdevptr.pcidev,0);
- if (!(candev->dev_base_addr = (long) ioremap(pita2_addr,
+ if (!(candev->aux_base_addr = ioremap(pita2_addr,
pci_resource_len(candev->sysdevptr.pcidev,0)))) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", pita2_addr);
goto error_ioremap_pita2;
}
io_addr=pci_resource_start(candev->sysdevptr.pcidev,1);;
- if (!(candev->io_addr = (long) ioremap(io_addr,
+ if (!(candev->dev_base_addr = ioremap(io_addr,
pci_resource_len(candev->sysdevptr.pcidev,1)))) {
CANMSG("Unable to access I/O memory at: 0x%lx\n", io_addr);
goto error_ioremap_io;
}
- candev->res_addr=candev->io_addr;
-
- /*
- * this is redundant with chip initialization, but remap address
+ candev->io_addr=io_addr;
+ candev->res_addr=pita2_addr;
+
+ /*
+ * this is redundant with chip initialization, but remap address
* can change when resources are temporarily released
*/
for(i=0;i<candev->nr_all_chips;i++) {
- struct chip_t *chip=candev->chip[i];
+ struct canchip_t *chip=candev->chip[i];
if(!chip) continue;
- chip->chip_base_addr = candev->io_addr+
+ chip->chip_base_addr = candev->dev_base_addr+
0x400 + i*EMS_CPCPCI_BYTES_PER_CIRCUIT;
if(!chip->msgobj[0]) continue;
chip->msgobj[0]->obj_base_addr=chip->chip_base_addr;
}
/* Configure PITA-2 parallel interface */
- writel(PITA2_MISC_CONFIG, candev->dev_base_addr + PITA2_MISC);
+ can_writel(PITA2_MISC_CONFIG, candev->aux_base_addr + PITA2_MISC);
ems_cpcpci_disconnect_irq(candev);
return 0;
error_ioremap_io:
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->aux_base_addr);
error_ioremap_pita2:
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
pci_release_region(candev->sysdevptr.pcidev, 1);
#else /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
pci_release_regions(candev->sysdevptr.pcidev);
#endif /*(LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))*/
-
+
return -ENODEV;
}
{
ems_cpcpci_disconnect_irq(candev);
- iounmap((void*)candev->io_addr);
- iounmap((void*)candev->dev_base_addr);
+ iounmap(candev->dev_base_addr);
+ iounmap(candev->aux_base_addr);
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,4,21))
pci_release_region(candev->sysdevptr.pcidev, 1);
pci_release_region(candev->sysdevptr.pcidev, 0);
}
-void ems_cpcpci_write_register(unsigned data, unsigned long address)
+void ems_cpcpci_write_register(unsigned data, can_ioptr_t address)
{
- address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
- *(EMS_CPCPCI_BYTES_PER_REG-1));
- writeb(data,address);
+ address += ((can_ioptr2ulong(address)&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
+ *(EMS_CPCPCI_BYTES_PER_REG-1));
+ can_writeb(data,address);
}
-unsigned ems_cpcpci_read_register(unsigned long address)
+unsigned ems_cpcpci_read_register(can_ioptr_t address)
{
- address += ((address&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
- *(EMS_CPCPCI_BYTES_PER_REG-1));
- return readb(address);
+ address += ((can_ioptr2ulong(address)&(EMS_CPCPCI_BYTES_PER_CIRCUIT-1))
+ *(EMS_CPCPCI_BYTES_PER_REG-1));
+ return can_readb(address);
}
-extern can_irqreturn_t sja1000p_irq_handler(int irq, void *dev_id, struct pt_regs *regs);
-
-can_irqreturn_t ems_cpcpci_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
+int ems_cpcpci_irq_handler(int irq, struct canchip_t *chip)
{
- struct chip_t *chip=(struct chip_t *)dev_id;
+ //struct canchip_t *chip=(struct canchip_t *)dev_id;
struct candevice_t *candev=chip->hostdevice;
int i;
unsigned long icr;
+ int test_irq_again;
+
+ icr=can_readl(candev->aux_base_addr + PITA2_ICR);
+ if(!(icr & PITA2_ICR_INT0)) return CANCHIP_IRQ_NONE;
- icr=readl(candev->dev_base_addr + PITA2_ICR);
- if(!(icr & PITA2_ICR_INT0)) return IRQ_NONE;
-
/* correct way to handle interrupts from all chips connected to the one PITA-2 */
do {
- writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->dev_base_addr + PITA2_ICR);
+ can_writel(PITA2_ICR_INT0_En | PITA2_ICR_INT0, candev->aux_base_addr + PITA2_ICR);
+ test_irq_again=0;
for(i=0;i<candev->nr_all_chips;i++){
chip=candev->chip[i];
if(!chip || !(chip->flags&CHIP_CONFIGURED))
continue;
- sja1000p_irq_handler(irq, dev_id, regs);
+ if(sja1000p_irq_handler(irq, chip))
+ test_irq_again=1;
}
- icr=readl(candev->dev_base_addr + PITA2_ICR);
- } while(icr & PITA2_ICR_INT0);
- return IRQ_HANDLED;
+ icr=can_readl(candev->aux_base_addr + PITA2_ICR);
+ } while((icr & PITA2_ICR_INT0)||test_irq_again);
+ return CANCHIP_IRQ_HANDLED;
}
int ems_cpcpci_reset(struct candevice_t *candev)
{
int i=0,chip_nr;
- struct chip_t *chip;
+ struct canchip_t *chip;
unsigned cdr;
DEBUGMSG("Resetting EMS_CPCPCI hardware ...\n");
ems_cpcpci_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
ems_cpcpci_write_register(0, chip->chip_base_addr+SJAIER);
-
+
ems_cpcpci_read_register(chip->chip_base_addr+SJAIR);
}
-
+
ems_cpcpci_connect_irq(candev);
return 0;
-}
+}
int ems_cpcpci_init_hw_data(struct candevice_t *candev)
{
- struct pci_dev *pcidev = NULL;
+ struct pci_dev *pcidev;
int i;
unsigned long l;
- pcidev = pci_find_device(EMS_CPCPCI_PCICAN_VENDOR, EMS_CPCPCI_PCICAN_ID, pcidev);
- if(pcidev == NULL) return -ENODEV;
-
+ pcidev = can_pci_get_next_untaken_device(EMS_CPCPCI_PCICAN_VENDOR, EMS_CPCPCI_PCICAN_ID);
+ if(pcidev == NULL)
+ return -ENODEV;
+
if (pci_enable_device (pcidev)){
printk(KERN_CRIT "Setup of EMS_CPCPCI failed\n");
+ can_pci_dev_put(pcidev);
return -EIO;
}
candev->sysdevptr.pcidev=pcidev;
-
+
for(i=0;i<2;i++){
if(!(pci_resource_flags(pcidev,0)&IORESOURCE_MEM)){
printk(KERN_CRIT "EMS_CPCPCI region %d is not memory\n",i);
+ can_pci_dev_put(pcidev);
return -EIO;
}
}
/*request IO access temporarily to check card presence*/
- if(ems_cpcpci_request_io(candev)<0)
+ if(ems_cpcpci_request_io(candev)<0) {
+ can_pci_dev_put(pcidev);
return -ENODEV;
+ }
- /*** candev->dev_base_addr=pci_resource_start(pcidev,0); ***/
+ /*** candev->aux_base_addr=pci_resource_start(pcidev,0); ***/
/* some control registers */
- /*** candev->io_addr=pci_resource_start(pcidev,1); ***/
+ /*** candev->dev_base_addr=pci_resource_start(pcidev,1); ***/
/* 0 more EMS control registers
* 0x400 the first SJA1000
* 0x600 the second SJA1000
* each register occupies 4 bytes
*/
-
+
/*candev->flags |= CANDEV_PROGRAMMABLE_IRQ;*/
-
+
for(l=0,i=0;i<4;i++){
l<<=8;
- l|=readb(candev->io_addr + i*4);
+ l|=can_readb(candev->dev_base_addr + i*4);
}
- i=readb(candev->io_addr + i*5);
-
+ i=can_readb(candev->dev_base_addr + i*5);
+
CANMSG("EMS CPC-PCI check value %04lx, ID %d\n", l, i);
-
+
if(l!=0x55aa01cb) {
CANMSG("EMS CPC-PCI unexpected check values\n");
}
candev->nr_all_chips=2;
ems_cpcpci_release_io(candev);
-
+
return 0;
}
+void ems_cpcpci_done_hw_data(struct candevice_t *candev)
+{
+ struct pci_dev *pcidev = candev->sysdevptr.pcidev;
+ can_pci_dev_put(pcidev);
+}
+
int ems_cpcpci_init_chip_data(struct candevice_t *candev, int chipnr)
{
if(candev->sysdevptr.pcidev==NULL)
/* initialize common routines for the SJA1000 chip */
sja1000p_fill_chipspecops(candev->chip[chipnr]);
-
+
/* special version of the IRQ handler is required for CPC-PCI board */
candev->chip[chipnr]->chipspecops->irq_handler=ems_cpcpci_irq_handler;
candev->chip[chipnr]->chip_irq=candev->sysdevptr.pcidev->irq;
- candev->chip[chipnr]->chip_base_addr = candev->io_addr+
+ candev->chip[chipnr]->chip_base_addr = candev->dev_base_addr+
0x400 + chipnr*EMS_CPCPCI_BYTES_PER_CIRCUIT;
candev->chip[chipnr]->flags = 0;
candev->chip[chipnr]->int_cpu_reg = 0;
candev->chip[chipnr]->flags |= CHIP_IRQ_PCI;
return 0;
-}
+}
-int ems_cpcpci_init_obj_data(struct chip_t *chip, int objnr)
+int ems_cpcpci_init_obj_data(struct canchip_t *chip, int objnr)
{
chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
return 0;
hwspecops->release_io = ems_cpcpci_release_io;
hwspecops->reset = ems_cpcpci_reset;
hwspecops->init_hw_data = ems_cpcpci_init_hw_data;
+ hwspecops->done_hw_data = ems_cpcpci_done_hw_data;
hwspecops->init_chip_data = ems_cpcpci_init_chip_data;
hwspecops->init_obj_data = ems_cpcpci_init_obj_data;
hwspecops->write_register = ems_cpcpci_write_register;
projects / lincan.git / blobdiff