+void c_can_registerdump(struct canchip_t *pchip)
+{
+ CANMSG("------------------------------------\n");
+ CANMSG("---------C-CAN Register Dump--------\n");
+ CANMSG("------------at 0x%.8lx-----------\n",
+ (unsigned long)pchip->chip_base_addr);
+ CANMSG("Control Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCCR)));
+ CANMSG("Status Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCSR)));
+ CANMSG("Error Counting Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCEC)));
+ CANMSG("Bit Timing Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCBT)));
+ CANMSG("Interrupt Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCINTR)));
+ CANMSG("Test Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCTR)));
+ CANMSG("Baud Rate Presc. Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCBRPE)));
+#ifdef C_CAN_WITH_CCCE
+ CANMSG("CAN Enable Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCCE)));
+#endif
+ CANMSG("Transm. Req. 1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCTREQ1)));
+ CANMSG("Transm. Req. 2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCTREQ2)));
+ CANMSG("New Data 1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCND1)));
+ CANMSG("New Data 2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCND2)));
+ CANMSG("Interrupt Pend. 1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCINTP1)));
+ CANMSG("Interrupt Pend. 2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCINTP2)));
+ CANMSG("------------------------------------\n");
+ CANMSG("IF1 Command Req. Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1CR)));
+ CANMSG("IF1 Command Mask Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1CM)));
+ CANMSG("IF1 Mask 1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1M1)));
+ CANMSG("IF1 Mask 2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1M2)));
+ CANMSG("IF1 Arbitration 1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1A1)));
+ CANMSG("IF1 Arbitration 2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1A2)));
+ CANMSG("IF1 Message Control Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1DMC)));
+ CANMSG("IF1 Data A1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1DA1)));
+ CANMSG("IF1 Data A2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1DA2)));
+ CANMSG("IF1 Data B1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1DB1)));
+ CANMSG("IF1 Data B2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF1DB2)));
+ CANMSG("------------------------------------\n");
+ CANMSG("IF2 Command Req. Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2CR)));
+ CANMSG("IF2 Command Mask Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2CM)));
+ CANMSG("IF2 Mask 1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2M1)));
+ CANMSG("IF2 Mask 2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2M2)));
+ CANMSG("IF2 Arbitration 1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2A1)));
+ CANMSG("IF2 Arbitration 2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2A2)));
+ CANMSG("IF2 Message Control Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2DMC)));
+ CANMSG("IF2 Data A1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2DA1)));
+ CANMSG("IF2 Data A2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2DA2)));
+ CANMSG("IF2 Data B1 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2DB1)));
+ CANMSG("IF2 Data B2 Register: 0x%.4lx\n",
+ (long)(c_can_read_reg_w(pchip, CCIF2DB2)));
+ CANMSG("------------------------------------\n");
+ CANMSG("------------------------------------\n");
+}
+
+void c_can_if1_registerdump(struct canchip_t *pchip)