Support for asynchronous SPI messages and callbacks

[lincan.git] / lincan / include / omap2_spican.h

diff --git a/lincan/include/omap2_spican.h b/lincan/include/omap2_spican.h
index c165a284fa90083d7b326d06a1735f50e9eb9c1e..6fae401ccc2c5c3f71f1c743a37f4e6f89fae8d0 100644 (file)
--- a/lincan/include/omap2_spican.h
+++ b/lincan/include/omap2_spican.h
@@ -6,7 +6,7 @@
  * Adapted for spican by Jan Kriz
  * email:devel@jojen.net
  * This software is released under the GPL-License.
- * Version lincan-0.3.4-r1  20 Aug 2010
+ * Version lincan-0.3.4-r2  14 Sep 2010
  */
 
 #define OMAP2_SPICAN_NCHIPS 1 // Since the device is initiated from SPI, it's applies to 1 chip (and 1 irq) at a time
@@ -32,16 +32,39 @@ int spican_program_irq(struct candevice_t *candev);
 #define OMAP2_SPICAN_DELAY_USECS (0)
 #define OMAP2_SPICAN_SPEED_HZ (10000000)
 
-struct omap2_spican_platform_data {
-       uint32_t mcp2515_clk; /* Clock frequency of MCP2515 */
-       uint32_t baudrate; /* Requested can communication speed */
+#define OMAP2_SPICAN_PRE_ASYNC (256)
+#define OMAP2_SPICAN_MAX_TRANSFERS (2)
+
+struct omap2_spican_async_t {
+       void (*complete)(void *arg, uint8_t count);
+       struct can_spi_async_t data[OMAP2_SPICAN_MAX_TRANSFERS];
+       uint8_t count;
+       uint8_t bitmap_bit;
+       struct spi_transfer t[OMAP2_SPICAN_MAX_TRANSFERS];
+       struct spi_message m;
+       uint8_t fasthandler;
+};
+
+struct lincan_spican_platform_data {
+       u32 clk; /* Clock frequency of the chip */
+       u32 baudrate; /* Requested can communication speed */
+       u32 speed_hz; /* Speed of SPI communication */
+       const char *chiptype;
        
-       unsigned cs_change; /* Cycle ~CS between transmissions? */
        u16 delay_usecs; /* Time gap between transmissions */
-       u32 speed_hz; /* Speed of SPI communication */
+       u8 cs_change; /* Cycle ~CS between transmissions? */
+};
 
+struct omap2_spican_platform_data {
+       /** This part must be kept the same as in struct lincan_spican_platform_data */
+       u32 clk; /* Clock frequency of the chip */
+       u32 baudrate; /* Requested can communication speed */
+       u32 speed_hz; /* Speed of SPI communication */
        const char *chiptype;
        
+       u16 delay_usecs; /* Time gap between transmissions */
+       u8 cs_change; /* Cycle ~CS between transmissions? */
+
        /* Following options are set at runtime */
        struct spi_device *spi; /* SPI device */
        u8      trigger;
@@ -51,6 +74,13 @@ struct omap2_spican_platform_data {
        int32_t timer_irq; // the IRQ # for our gp timer
 #endif /* CONFIG_OMAP_DM_TIMER */
        spinlock_t spi_lock;
+       struct omap2_spican_async_t async[OMAP2_SPICAN_PRE_ASYNC];
+       DECLARE_BITMAP(async_req_map, OMAP2_SPICAN_PRE_ASYNC);
+       DECLARE_BITMAP(lo_async_done_map, OMAP2_SPICAN_PRE_ASYNC);
+       struct tasklet_struct lo_async_tasklet;
+       struct work_struct lo_async_workqueue;
+       DECLARE_BITMAP(hi_async_done_map, OMAP2_SPICAN_PRE_ASYNC);
+       struct tasklet_struct hi_async_tasklet;
 };
 
 int omap2_spican_init(void);