]> rtime.felk.cvut.cz Git - lincan.git/blobdiff - embedded/app/usbcan/can.c
The simulated data bus access on target simplified.
[lincan.git] / embedded / app / usbcan / can.c
index 25d7f343f0762fa97db3303050ffa12b92fd94ee..fc945993b177faa9f72e015adfe9217477c3087f 100644 (file)
@@ -11,22 +11,37 @@ See documentation for details.
 
 #include "can/can.h"
 
-/// Baud rates
-#if SJA1000_CLK==(24000000)
-       /*      Bus speed, Precaler, SJW, TSEG1, TSEG2
-        *      For SJW setting we assume 1% xtal accuracy
+inline void can_data_pins_dir_output(void)
+{
+       IO1DIR|=P1_SJA1000_DATA_PINS; // Port as output to send data
+}
+
+inline void can_data_pins_dir_input(void)
+{
+       IO1DIR&=~P1_SJA1000_DATA_PINS; // Sets port as input
+}
+
+inline void can_data_pins_set_value(uint8_t data)
+{
+       uint32_t val = __val2mfld(P1_SJA1000_DATA_PINS,data);
+       /*
+        * Clear only that pins, which need that, lower transition
+        * frequency and eliminate spikes
         */
-       const long sja1000_freqs[3][5]=
-       {{1000, 0x00,   0xC0,   0x08,   0x10}
-       ,{250,  0x02,   0xC0,   0x0A,   0x30}
-       ,{100,  0x07,   0xC0,   0x09,   0x30}};
-       const int sja1000_freq_cnt=3;
-#endif
+       IO1CLR= val ^ P1_SJA1000_DATA_PINS;
+       IO1SET= val;
+}
+
+inline uint8_t can_data_pins_get_value(void)
+{
+       return __mfld2val(P1_SJA1000_DATA_PINS,IO1PIN);
+}
 
-struct can_baudparams_t canbaud;
 
 void can_comm_init()
 {
+       //CANMSG("Start can_comm_init\n");
+       IO1DIR |= P1_OUT_PORT_CS_PIN|P1_SJA1000_RST_PIN;
        // Due to change in design there is CS_PIN connected with ALE_PIN and ALE_PIN connection to LPC is interrupted
        // We don't use ALE_PIN
        //IO0DIR|=P0_SJA1000_ALE_PIN|P0_SJA1000_CS_PIN|P0_SJA1000_RD_PIN|P0_SJA1000_WR_PIN;
@@ -43,94 +58,95 @@ void can_comm_init()
        SJA1000_INIT_DELAY();
 }
 
-int can_write(uint8_t address,uint8_t* data)
+void can_write(uint8_t data, uint8_t address)
 {
-       IO1DIR|=0x00FF0000; // Port as output to send data
-       IO1CLR=0x00FF0000; // Clear all data on port
+       can_data_pins_dir_output();
+       // Set memory address
+       can_data_pins_set_value(address);
        // Init
        SET_OUT_PIN(IO0,P0_SJA1000_RD_PIN);     // Stays high on write
        SET_OUT_PIN(IO0,P0_SJA1000_WR_PIN); // Stays high on address write
        SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN); // Sets output buffers to third state
-       SJA1000_DELAY();
+       //SJA1000_DELAY();
        //SET_OUT_PIN(IO0,P0_SJA1000_ALE_PIN); // Start command
 
-       // Set memory address
-       IO1SET=__val2mfld(0x00FF0000,address); // Shift data to SJA pins and output them
-       SJA1000_DELAY();
+       //SJA1000_DELAY();
        //CLR_OUT_PIN(IO0,P0_SJA1000_ALE_PIN); // Makes address active
        CLR_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
-       SJA1000_DELAY();
+       //SJA1000_DELAY();
 
        // Setting data
-       CLR_OUT_PIN(IO0,P0_SJA1000_WR_PIN);
+       can_data_pins_set_value(data);
 
-       IO1CLR=0x00FF0000;
-       IO1SET=__val2mfld(0x00FF0000,*data);
-       SJA1000_DELAY();
+       CLR_OUT_PIN(IO0,P0_SJA1000_WR_PIN);
+       CLR_OUT_PIN(IO0,P0_SJA1000_WR_PIN);
+       //SJA1000_DELAY();
        SET_OUT_PIN(IO0,P0_SJA1000_WR_PIN); // Data should be accepted by now
        SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
-       SJA1000_DELAY();
-       return 0;
+       //SJA1000_DELAY();
 }
 
-int can_read(const uint8_t address,uint8_t* data)
+uint8_t can_read(const uint8_t address)
 {
-       IO1DIR|=0x00FF0000; // Port as output to set address
-       IO1CLR=0x00FF0000; // Clear all data
+       uint8_t data;
+
+       can_data_pins_dir_output();
+       // Set memory address
+       can_data_pins_set_value(address);
        // Init
        SET_OUT_PIN(IO0,P0_SJA1000_WR_PIN); // Stays high on read
        SET_OUT_PIN(IO0,P0_SJA1000_RD_PIN); // Stays high while entering address
        SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
-       SJA1000_DELAY();
+       //SJA1000_DELAY();
        //SET_OUT_PIN(IO0,P0_SJA1000_ALE_PIN);
 
-       // Request memory address
-       IO1SET=__val2mfld(0x00FF0000,address);
-       SJA1000_DELAY();
+       //SJA1000_DELAY();
        //CLR_OUT_PIN(IO0,P0_SJA1000_ALE_PIN);
        CLR_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
 
        // Get data
 
-       IO1DIR&=~0x00FF0000; // Sets port as input
+       can_data_pins_dir_input();
+       CLR_OUT_PIN(IO0,P0_SJA1000_RD_PIN);
        CLR_OUT_PIN(IO0,P0_SJA1000_RD_PIN);
-       SJA1000_DELAY();
-       *data=__mfld2val(0x00FF0000,IO1PIN);
+       //SJA1000_DELAY();
+       data = can_data_pins_get_value();
        SET_OUT_PIN(IO0,P0_SJA1000_RD_PIN);
        SET_OUT_PIN(IO0,P0_SJA1000_CS_PIN);
-       SJA1000_DELAY();
-       return 0;
+       //SJA1000_DELAY();
+
+       return data;
 }
 
 int can_init(){
        uint8_t data=0,count=0;
        do {
                can_comm_init();
-               can_read(SJAMOD,&data);
+               data = can_read(SJAMOD);
                if (count++ > 50)
                        return -1;
        } while (!(data&sjaMOD_RM));
 
        data=sjaCDR_CLKOUT_DIV1|sjaCDR_CLK_OFF|sjaCDR_CBP|sjaCDR_PELICAN;
-       can_write((uint8_t)SJACDR,(uint8_t*)&data);
+       can_write(data, SJACDR);
 
        // Single acceptance filter, reset mode
        data=sjaMOD_AFM|sjaMOD_RM;
-       can_write((uint8_t)SJAMOD,(uint8_t*)&data);
+       can_write(data, SJAMOD);
 
        // Enabling all interrupt sources
        data=sjaENABLE_INTERRUPTS;
-       can_write((uint8_t)SJAIER,(uint8_t*)&data);
+       can_write(data, SJAIER);
 
        // Accept all messages
        data=0xFF;
-       can_write((uint8_t)SJAAMR0,(uint8_t*)&data);
-       can_write((uint8_t)SJAAMR0+1,(uint8_t*)&data);
-       can_write((uint8_t)SJAAMR0+2,(uint8_t*)&data);
-       can_write((uint8_t)SJAAMR0+3,(uint8_t*)&data);
+       can_write(data, SJAAMR0);
+       can_write(data, SJAAMR0+1);
+       can_write(data, SJAAMR0+2);
+       can_write(data, SJAAMR0+3);
 
        data=sjaCMR_CDO;
-       can_write((uint8_t)SJACMR,(uint8_t*)&data);
+       can_write(data, SJACMR);
 
        return 0;
 }