can_outb(0x00,candev->res_addr);
}
outb_p(0x01,candev->res_addr);
can_outb(0x00,candev->res_addr);
}
outb_p(0x01,candev->res_addr);
can_outb(0x00,candev->chip[2]->chip_base_addr+SJACR);
can_outb(0x00,candev->chip[3]->chip_base_addr+SJACR);
can_outb(0x00,candev->chip[2]->chip_base_addr+SJACR);
can_outb(0x00,candev->chip[3]->chip_base_addr+SJACR);
DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
}
for (chip_nr=2; chip_nr<4; chip_nr++) {
i=0;
while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
SJACR) & sjaCR_RR) && (i<=15) ) {
DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
}
for (chip_nr=2; chip_nr<4; chip_nr++) {
i=0;
while( (can_inb(candev->chip[chip_nr]->chip_base_addr +
SJACR) & sjaCR_RR) && (i<=15) ) {
candev->chip[chipnr]->int_clk_reg=iCLK_SL1;
candev->chip[chipnr]->int_bus_reg=iBUS_CBY;
candev->chip[chipnr]->sja_cdr_reg = 0;
candev->chip[chipnr]->int_clk_reg=iCLK_SL1;
candev->chip[chipnr]->int_bus_reg=iBUS_CBY;
candev->chip[chipnr]->sja_cdr_reg = 0;
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CLK_OFF;
candev->chip[chipnr]->int_clk_reg = 0;
candev->chip[chipnr]->int_bus_reg = 0;
candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CLK_OFF;