JAILHOUSE_CPU_STATS_ATTR(vmexits_msr, JAILHOUSE_CPU_STAT_VMEXITS_MSR);
JAILHOUSE_CPU_STATS_ATTR(vmexits_cpuid, JAILHOUSE_CPU_STAT_VMEXITS_CPUID);
JAILHOUSE_CPU_STATS_ATTR(vmexits_xsetbv, JAILHOUSE_CPU_STAT_VMEXITS_XSETBV);
+#elif defined(CONFIG_ARM)
+JAILHOUSE_CPU_STATS_ATTR(vmexits_maintenance, JAILHOUSE_CPU_STAT_VMEXITS_MAINTENANCE);
+JAILHOUSE_CPU_STATS_ATTR(vmexits_virt_irq, JAILHOUSE_CPU_STAT_VMEXITS_VIRQ);
+JAILHOUSE_CPU_STATS_ATTR(vmexits_virt_sgi, JAILHOUSE_CPU_STAT_VMEXITS_VSGI);
#endif
static struct attribute *no_attrs[] = {
&vmexits_msr_attr.kattr.attr,
&vmexits_cpuid_attr.kattr.attr,
&vmexits_xsetbv_attr.kattr.attr,
+#elif defined(CONFIG_ARM)
+ &vmexits_maintenance_attr.kattr.attr,
+ &vmexits_virt_irq_attr.kattr.attr,
+ &vmexits_virt_sgi_attr.kattr.attr,
#endif
NULL
};
struct registers* arch_handle_exit(struct per_cpu *cpu_data,
struct registers *regs)
{
+ cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_TOTAL]++;
+
switch (regs->exit_reason) {
case EXIT_REASON_IRQ:
irqchip_handle_irq(cpu_data);
void arch_handle_sgi(struct per_cpu *cpu_data, u32 irqn)
{
+ cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MANAGEMENT]++;
+
switch (irqn) {
case SGI_INJECT:
irqchip_inject_pending(cpu_data);
bool arch_handle_phys_irq(struct per_cpu *cpu_data, u32 irqn)
{
if (irqn == MAINTENANCE_IRQ) {
+ cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MAINTENANCE]++;
+
irqchip_inject_pending(cpu_data);
return true;
}
+ cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_VIRQ]++;
+
irqchip_set_pending(cpu_data, irqn, true);
return false;
struct cell *cell = cpu_data->cell;
bool is_target = false;
+ cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_VSGI]++;
+
targets = sgi->targets;
sgi->targets = 0;
#define JAILHOUSE_CALL_ARG2 "r2"
/* CPU statistics */
-#define JAILHOUSE_NUM_CPU_STATS JAILHOUSE_GENERIC_CPU_STATS
+#define JAILHOUSE_CPU_STAT_VMEXITS_MAINTENANCE JAILHOUSE_GENERIC_CPU_STATS
+#define JAILHOUSE_CPU_STAT_VMEXITS_VIRQ JAILHOUSE_GENERIC_CPU_STATS + 1
+#define JAILHOUSE_CPU_STAT_VMEXITS_VSGI JAILHOUSE_GENERIC_CPU_STATS + 2
+#define JAILHOUSE_NUM_CPU_STATS JAILHOUSE_GENERIC_CPU_STATS + 3
#ifndef __asmeq
#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
access.addr = hpfar << 8;
access.addr |= hdfar & 0xfff;
+ cpu_data->stats[JAILHOUSE_CPU_STAT_VMEXITS_MMIO]++;
+
/*
* Invalid instruction syndrome means multiple access or writeback, there
* is nothing we can do.