arm: Fix spi_in_cell for SPIs 32..63

The cell configuration format restricts us to 64 SPIs this far. Make
sure that we properly test the range of 32 to 63 and avoid overflows due
to 32-bit word width. As Jailhouse provides no __aeabi_llsr, extract
high and low words first, then scan within 32 bits.

This addresses Coverity finding CID 21110.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/arch/arm/include/asm/irqchip.h b/hypervisor/arch/arm/include/asm/irqchip.h
index 0f573fd68dbbf46efa00df8624df36141549cd38..1f1ae5467d32d5af3339924cac1a793d874ec871 100644 (file)
--- a/hypervisor/arch/arm/include/asm/irqchip.h
+++ b/hypervisor/arch/arm/include/asm/irqchip.h
@@ -105,14 +105,16 @@ int irqchip_set_pending(struct per_cpu *cpu_data, u32 irq_id, bool try_inject);
 static inline bool spi_in_cell(struct cell *cell, unsigned int spi)
 {
        /* FIXME: Change the configuration to a bitmask range */
-       u64 spi_mask;
+       u32 spi_mask;
 
-       if (spi > 64)
+       if (spi >= 64)
                return false;
+       else if (spi >= 32)
+               spi_mask = cell->arch.spis >> 32;
+       else
+               spi_mask = cell->arch.spis;
 
-       spi_mask = cell->arch.spis;
-
-       return spi_mask & (1 << spi);
+       return spi_mask & (1 << (spi & 31));
 }
 
 #endif /* __ASSEMBLY__ */