x86: Make SMI filter feature test of AMD IOMMU stricter

The only valid value of SmiFSup we are aware of is 01b.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/arch/x86/amd_iommu.c b/hypervisor/arch/x86/amd_iommu.c
index 31e78f4b6d7317be5a071013f1e56d73315a4a43..fb2f952fd7a1d7759dcf5f7f50bec48b7e675e73 100644 (file)
--- a/hypervisor/arch/x86/amd_iommu.c
+++ b/hypervisor/arch/x86/amd_iommu.c
@@ -50,8 +50,8 @@
 #define  AMD_CONTROL_SEG_EN_SHIFT      34
 #define AMD_EXT_FEATURES_REG           0x0030
 #define  AMD_EXT_FEAT_HE_SUP           (1UL << 7)
+#define  AMD_EXT_FEAT_SMI_FSUP         (1UL << 16)
 #define  AMD_EXT_FEAT_SMI_FSUP_MASK    BIT_MASK(17, 16)
-#define  AMD_EXT_FEAT_SMI_FSUP_SHIFT   16
 #define  AMD_EXT_FEAT_SMI_FRC_MASK     BIT_MASK(20, 18)
 #define  AMD_EXT_FEAT_SMI_FRC_SHIFT    18
 #define  AMD_EXT_FEAT_SEG_SUP_MASK     BIT_MASK(39, 38)
@@ -222,8 +222,8 @@ static int amd_iommu_init_features(struct amd_iommu *entry,
         * Require SMI Filter support. Enable and lock filter but
         * mark all entries as invalid to disable SMI delivery.
         */
-       if (!(efr & AMD_EXT_FEAT_SMI_FSUP_MASK))
-               return trace_error(-EINVAL);
+       if ((efr & AMD_EXT_FEAT_SMI_FSUP_MASK) != AMD_EXT_FEAT_SMI_FSUP)
+               return trace_error(-EIO);
 
        /* Figure out if hardware events are supported. */
        if (iommu->amd_features)