core, tools: Add BAR masks to jailhouse_pci_device

Add a new field per BAR to the PCI device configuration. It allows to
mask the modifiable part of a BAR before storing writes. This will
support BAR write emulation that is required to make PCI resource sizes
explorable by cells.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/include/jailhouse/cell-config.h b/hypervisor/include/jailhouse/cell-config.h
index 94c4996d9edb3abba696a3cdd7b61680d25eb2a9..261d9c74b29a1c19c0bad5d1388f28bc6c876e0e 100644 (file)
--- a/hypervisor/include/jailhouse/cell-config.h
+++ b/hypervisor/include/jailhouse/cell-config.h
@@ -95,6 +95,7 @@ struct jailhouse_pci_device {
        __u8 iommu;
        __u16 domain;
        __u16 bdf;
+       __u32 bar_mask[6];
        __u16 caps_start;
        __u16 num_caps;
        __u8 num_msi_vectors;

diff --git a/tools/jailhouse-config-create b/tools/jailhouse-config-create
index c4b74b837962773a050caa13ccc203ec1fb606d5..0b41cf9015be082a1cbf9871262d1352f27cebd7 100755 (executable)
--- a/tools/jailhouse-config-create
+++ b/tools/jailhouse-config-create
@@ -82,6 +82,7 @@ inputs['files'].add('/proc/cpuinfo')
 inputs['files'].add('/proc/cmdline')
 inputs['files'].add('/proc/ioports')
 inputs['files'].add('/sys/bus/pci/devices/*/config')
+inputs['files'].add('/sys/bus/pci/devices/*/resource')
 inputs['files'].add('/sys/devices/system/cpu/cpu*/uevent')
 inputs['files'].add('/sys/firmware/acpi/tables/APIC')
 inputs['files'].add('/sys/firmware/acpi/tables/MCFG')
@@ -153,6 +154,30 @@ def input_listdir(dir, wildcards):
     return dirs
 
 
+class PCIBARs:
+    IORESOURCE_IO = 0x00000100
+    IORESOURCE_MEM = 0x00000200
+    IORESOURCE_MEM_64 = 0x00100000
+
+    def __init__(self, dir):
+        self.mask = []
+        f = input_open(os.path.join(dir, 'resource'), 'r')
+        for n in range(6):
+            (start, end, flags) = f.readline().split()
+            flags = int(flags, 16)
+            if flags & PCIBARs.IORESOURCE_IO:
+                mask = ~(int(end, 16) - int(start, 16))
+            elif flags & PCIBARs.IORESOURCE_MEM:
+                mask = ~(int(end, 16) - int(start, 16))
+                if flags & PCIBARs.IORESOURCE_MEM_64:
+                    self.mask.append(mask & 0xffffffff)
+                    mask >>= 32
+                    n += 1
+            else:
+                mask = 0
+            self.mask.append(mask & 0xffffffff)
+        f.close()
+
 class PCICapability:
     def __init__(self, id, start, len, flags, content, msix_address):
         self.id = id
@@ -226,13 +251,14 @@ class PCICapability:
 
 
 class PCIDevice:
-    def __init__(self, type, domain, bus, dev, fn, caps, path):
+    def __init__(self, type, domain, bus, dev, fn, bars, caps, path):
         self.type = type
         self.iommu = None
         self.domain = domain
         self.bus = bus
         self.dev = dev
         self.fn = fn
+        self.bars = bars
         self.caps = caps
         self.path = path
         self.caps_start = 0
@@ -279,9 +305,10 @@ class PCIDevice:
         domain = int(a[0], 16)
         bus = int(a[1], 16)
         df = a[2].split('.')
+        bars = PCIBARs(dpath)
         caps = PCICapability.parse_pcicaps(dpath)
         return PCIDevice(type, domain, bus, int(df[0], 16), int(df[1], 16),
-                         caps, dpath)
+                         bars, caps, dpath)
 
 
 class PCIPCIBridge(PCIDevice):

diff --git a/tools/root-cell-config.c.tmpl b/tools/root-cell-config.c.tmpl
index 51f2f47e93d8b6f9b51a4180d1000bca627a73bf..fdf8f8b6bfb1f0afe2f0fb95dac9a69cf6029500 100644 (file)
--- a/tools/root-cell-config.c.tmpl
+++ b/tools/root-cell-config.c.tmpl
@@ -143,6 +143,10 @@ struct {
                        % endif
                        .domain = ${hex(d.domain)},
                        .bdf = ${hex(d.bdf())},
+                       .bar_mask = {
+                               ${'0x%08x' % d.bars.mask[0]}, ${'0x%08x' % d.bars.mask[1]}, ${'0x%08x' % d.bars.mask[2]},
+                               ${'0x%08x' % d.bars.mask[3]}, ${'0x%08x' % d.bars.mask[4]}, ${'0x%08x' % d.bars.mask[5]},
+                       },
                        .caps_start = ${d.caps_start},
                        .num_caps = ${d.num_caps},
                        .num_msi_vectors = ${d.num_msi_vectors},