core: Tag PCI express extended capability IDs via highest bit

PCI express extended capabilities span a separate ID space. In order to
use the same jailhouse_pci_capability structure as for PCI capabilities
and also to avoid extending the ID field, reserve the highest bit 15 to
tag extended IDs. PCI so far only uses the lowest 5 bits and apparently
expands linearly, so we won't see any conflicts in the foreseeable
future.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/include/jailhouse/cell-config.h b/hypervisor/include/jailhouse/cell-config.h
index ef9de707af05e8f1f852c24548b3d06b6380f1c1..a6315a3012a7e2d7a08c90611bf24a6207be7287 100644 (file)
--- a/hypervisor/include/jailhouse/cell-config.h
+++ b/hypervisor/include/jailhouse/cell-config.h
@@ -110,6 +110,8 @@ struct jailhouse_pci_device {
        __u32 shmem_region;
 } __attribute__((packed));
 
+#define JAILHOUSE_PCI_EXT_CAP          0x8000
+
 #define JAILHOUSE_PCICAPS_WRITE                0x0001
 
 struct jailhouse_pci_capability {