x86: Enable APIC for clearing

The cell may have turned it off, and then our attempts to clear pending
interrupts will be in vain.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>

diff --git a/hypervisor/arch/x86/apic.c b/hypervisor/arch/x86/apic.c
index f514943c5f338e78b56d039d94dea63ac6dca040..1cfd543534ce79be3c22fe5a7d4b5b8b6fb87373 100644 (file)
--- a/hypervisor/arch/x86/apic.c
+++ b/hypervisor/arch/x86/apic.c
@@ -295,6 +295,9 @@ void apic_clear(void)
        unsigned int xlc = (apic_ext_features() >> 16) & 0xff;
        int n;
 
+       /* Enable the APIC - the cell may have turned it off */
+       apic_ops.write(APIC_REG_SVR, APIC_SVR_ENABLE_APIC | 0xff);
+
        /* Mask all available LVTs */
        apic_mask_lvt(APIC_REG_LVTERR);
        if (maxlvt >= 6)

diff --git a/hypervisor/arch/x86/include/asm/apic.h b/hypervisor/arch/x86/include/asm/apic.h
index 9c7ca12b6cde896163b58b552b361a875d823abc..27a4eef6ee57b4757afbf0462495c6253d2d4072 100644 (file)
--- a/hypervisor/arch/x86/include/asm/apic.h
+++ b/hypervisor/arch/x86/include/asm/apic.h
@@ -34,6 +34,7 @@
 #define APIC_REG_EOI                   0x0b
 #define APIC_REG_LDR                   0x0d
 #define APIC_REG_DFR                   0x0e
+#define APIC_REG_SVR                   0x0f
 #define APIC_REG_ISR0                  0x10
 #define APIC_REG_LVTCMCI               0x2f
 #define APIC_REG_ICR                   0x30
@@ -50,6 +51,7 @@
 #define APIC_REG_XLVT3                 0x53
 
 #define APIC_EOI_ACK                   0
+#define APIC_SVR_ENABLE_APIC           0x00000100
 #define APIC_ICR_VECTOR_MASK           0x000000ff
 #define APIC_ICR_DLVR_MASK             0x00000700
 #define APIC_ICR_DLVR_SHIFT            8