2 * Jailhouse, a Linux-based partitioning hypervisor
4 * Copyright (c) ARM Limited, 2014
7 * Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
13 #include <jailhouse/control.h>
14 #include <jailhouse/mmio.h>
15 #include <asm/gic_common.h>
16 #include <asm/irqchip.h>
17 #include <asm/platform.h>
18 #include <asm/setup.h>
20 static unsigned int gic_num_lr;
22 extern void *gicd_base;
23 extern unsigned int gicd_size;
25 unsigned int gicc_size;
28 unsigned int gich_size;
30 static int gic_init(void)
34 /* FIXME: parse device tree */
35 gicc_base = GICC_BASE;
36 gicc_size = GICC_SIZE;
37 gich_base = GICH_BASE;
38 gich_size = GICH_SIZE;
39 gicv_base = GICV_BASE;
41 err = arch_map_device(gicc_base, gicc_base, gicc_size);
45 err = arch_map_device(gich_base, gich_base, gich_size);
50 static void gic_clear_pending_irqs(void)
54 /* Clear list registers. */
55 for (n = 0; n < gic_num_lr; n++)
58 /* Clear active priority bits. */
59 mmio_write32(gich_base + GICH_APR, 0);
62 static int gic_cpu_reset(struct per_cpu *cpu_data, bool is_shutdown)
65 bool root_shutdown = is_shutdown && (cpu_data->cell == &root_cell);
68 u32 gicc_ctlr, gicc_pmr;
70 gic_clear_pending_irqs();
72 /* Deactivate all PPIs */
73 active = mmio_read32(gicd_base + GICD_ISACTIVER);
74 for (i = 16; i < 32; i++) {
75 if (test_bit(i, (unsigned long *)&active))
76 mmio_write32(gicc_base + GICC_DIR, i);
79 /* Disable PPIs if necessary */
81 mmio_write32(gicd_base + GICD_ICENABLER, 0xffff0000);
82 /* Ensure IPIs are enabled */
83 mmio_write32(gicd_base + GICD_ISENABLER, 0x0000ffff);
86 mmio_write32(gich_base + GICH_HCR, 0);
89 gich_vmcr = mmio_read32(gich_base + GICH_VMCR);
91 gicc_pmr = (gich_vmcr >> GICH_VMCR_PMR_SHIFT) << GICV_PMR_SHIFT;
93 if (gich_vmcr & GICH_VMCR_EN0)
94 gicc_ctlr |= GICC_CTLR_GRPEN1;
95 if (gich_vmcr & GICH_VMCR_EOImode)
96 gicc_ctlr |= GICC_CTLR_EOImode;
98 mmio_write32(gicc_base + GICC_CTLR, gicc_ctlr);
99 mmio_write32(gicc_base + GICC_PMR, gicc_pmr);
103 mmio_write32(gich_base + GICH_VMCR, gich_vmcr);
108 static int gic_cpu_init(struct per_cpu *cpu_data)
111 u32 cell_gicc_ctlr, cell_gicc_pmr;
113 /* Ensure all IPIs are enabled */
114 mmio_write32(gicd_base + GICD_ISENABLER, 0x0000ffff);
116 cell_gicc_ctlr = mmio_read32(gicc_base + GICC_CTLR);
117 cell_gicc_pmr = mmio_read32(gicc_base + GICC_PMR);
119 mmio_write32(gicc_base + GICC_CTLR,
120 GICC_CTLR_GRPEN1 | GICC_CTLR_EOImode);
121 mmio_write32(gicc_base + GICC_PMR, GICC_PMR_DEFAULT);
123 vtr = mmio_read32(gich_base + GICH_VTR);
124 gic_num_lr = (vtr & 0x3f) + 1;
126 /* VMCR only contains 5 bits of priority */
127 vmcr = (cell_gicc_pmr >> GICV_PMR_SHIFT) << GICH_VMCR_PMR_SHIFT;
129 * All virtual interrupts are group 0 in this driver since the GICV
130 * layout seen by the guest corresponds to GICC without security
132 * - A read from GICV_IAR doesn't acknowledge group 1 interrupts
133 * (GICV_AIAR does it, but the guest never attempts to accesses it)
134 * - A write to GICV_CTLR.GRP0EN corresponds to the GICC_CTLR.GRP1EN bit
135 * Since the guest's driver thinks that it is accessing a GIC with
136 * security extensions, a write to GPR1EN will enable group 0
138 * - Group 0 interrupts are presented as virtual IRQs (FIQEn = 0)
140 if (cell_gicc_ctlr & GICC_CTLR_GRPEN1)
141 vmcr |= GICH_VMCR_EN0;
142 if (cell_gicc_ctlr & GICC_CTLR_EOImode)
143 vmcr |= GICH_VMCR_EOImode;
145 mmio_write32(gich_base + GICH_VMCR, vmcr);
146 mmio_write32(gich_base + GICH_HCR, GICH_HCR_EN);
149 * Clear pending virtual IRQs in case anything is left from previous
150 * use. Physically pending IRQs will be forwarded to Linux once we
151 * enable interrupts for the hypervisor.
153 gic_clear_pending_irqs();
155 /* Register ourselves into the CPU itf map */
156 gic_probe_cpu_id(cpu_data->cpu_id);
161 static void gic_eoi_irq(u32 irq_id, bool deactivate)
164 * The GIC doesn't seem to care about the CPUID value written to EOIR,
165 * which is rather convenient...
167 mmio_write32(gicc_base + GICC_EOIR, irq_id);
169 mmio_write32(gicc_base + GICC_DIR, irq_id);
172 static int gic_cell_init(struct cell *cell)
177 * target_cpu_map has not been populated by all available CPUs when the
178 * setup code initialises the root cell. It is assumed that the kernel
179 * already has configured all its SPIs anyway, and that it will redirect
180 * them when unplugging a CPU.
182 if (cell != &root_cell)
183 gic_target_spis(cell, cell);
186 * Let the guest access the virtual CPU interface instead of the
189 * WARN: some SoCs (EXYNOS4) use a modified GIC which doesn't have any
190 * banked CPU interface, so we should map per-CPU physical addresses
192 * As for now, none of them seem to have virtualization extensions.
194 err = paging_create(&cell->arch.mm, (unsigned long)gicv_base,
195 gicc_size, (unsigned long)gicc_base,
196 (PTE_FLAG_VALID | PTE_ACCESS_FLAG |
197 S2_PTE_ACCESS_RW | S2_PTE_FLAG_DEVICE),
198 PAGING_NON_COHERENT);
202 mmio_region_register(cell, (unsigned long)gicd_base, gicd_size,
203 gic_handle_dist_access, NULL);
207 static void gic_cell_exit(struct cell *cell)
209 paging_destroy(&cell->arch.mm, (unsigned long)gicc_base, gicc_size,
210 PAGING_NON_COHERENT);
211 /* Reset interrupt routing of the cell's spis */
212 gic_target_spis(cell, &root_cell);
215 static int gic_send_sgi(struct sgi *sgi)
219 if (!is_sgi(sgi->id))
222 val = (sgi->routing_mode & 0x3) << 24
223 | (sgi->targets & 0xff) << 16
226 mmio_write32(gicd_base + GICD_SGIR, val);
231 static int gic_inject_irq(struct per_cpu *cpu_data, struct pending_irq *irq)
236 unsigned long elsr[2];
238 elsr[0] = mmio_read32(gich_base + GICH_ELSR0);
239 elsr[1] = mmio_read32(gich_base + GICH_ELSR1);
240 for (i = 0; i < gic_num_lr; i++) {
241 if (test_bit(i, elsr)) {
242 /* Entry is available */
243 if (first_free == -1)
248 /* Check that there is no overlapping */
250 if ((lr & GICH_LR_VIRT_ID_MASK) == irq->virt_id)
254 if (first_free == -1)
257 /* Inject group 0 interrupt (seen as IRQ by the guest) */
259 lr |= GICH_LR_PENDING_BIT;
261 if (!is_sgi(irq->virt_id)) {
262 lr |= GICH_LR_HW_BIT;
263 lr |= irq->virt_id << GICH_LR_PHYS_ID_SHIFT;
266 gic_write_lr(first_free, lr);
271 static void gic_enable_maint_irq(bool enable)
275 hcr = mmio_read32(gich_base + GICH_HCR);
279 hcr &= ~GICH_HCR_UIE;
280 mmio_write32(gich_base + GICH_HCR, hcr);
283 unsigned int irqchip_mmio_count_regions(struct cell *cell)
288 struct irqchip_ops gic_irqchip = {
290 .cpu_init = gic_cpu_init,
291 .cpu_reset = gic_cpu_reset,
292 .cell_init = gic_cell_init,
293 .cell_exit = gic_cell_exit,
295 .send_sgi = gic_send_sgi,
296 .handle_irq = gic_handle_irq,
297 .inject_irq = gic_inject_irq,
298 .enable_maint_irq = gic_enable_maint_irq,
299 .eoi_irq = gic_eoi_irq,