hypervisor/arch/x86/dbg-write.c

   1 /*
   2  * Jailhouse, a Linux-based partitioning hypervisor
   3  *
   4  * Copyright (c) Siemens AG, 2013
   5  *
   6  * Authors:
   7  *  Jan Kiszka <jan.kiszka@siemens.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2.  See
  10  * the COPYING file in the top-level directory.
  11  */
  12
  13 #include <jailhouse/printk.h>
  14 #include <jailhouse/processor.h>
  15 #include <asm/io.h>
  16
  17 #ifdef CONFIG_UART_OXPCIE952
  18 #define UART_BASE               0xe010
  19 #else
  20 //it was changed for fiasco use-case (default 0x3f8)
  21 #define UART_BASE               0x2f8
  22 #endif
  23 #define  UART_TX                0x0
  24 #define  UART_DLL               0x0
  25 #define  UART_DLM               0x1
  26 #define  UART_LCR               0x3
  27 #define  UART_LCR_8N1           0x03
  28 #define  UART_LCR_DLAB          0x80
  29 #define  UART_LSR               0x5
  30 #define  UART_LSR_THRE          0x20
  31
  32 void arch_dbg_write_init(void)
  33 {
  34         outb(UART_LCR_DLAB, UART_BASE + UART_LCR);
  35 #ifdef CONFIG_UART_OXPCIE952
  36         outb(0x22, UART_BASE + UART_DLL);
  37 #else
  38         outb(1, UART_BASE + UART_DLL);
  39 #endif
  40         outb(0, UART_BASE + UART_DLM);
  41         outb(UART_LCR_8N1, UART_BASE + UART_LCR);
  42 }
  43
  44 void arch_dbg_write(const char *msg)
  45 {
  46         char c = 0;
  47
  48         while (1) {
  49                 if (c == '\n')
  50                         c = '\r';
  51                 else
  52                         c = *msg++;
  53                 if (!c)
  54                         break;
  55                 while (!(inb(UART_BASE + UART_LSR) & UART_LSR_THRE))
  56                         cpu_relax();
  57                 if (panic_in_progress && panic_cpu != phys_processor_id())
  58                         break;
  59                 outb(c, UART_BASE + UART_TX);
  60         }
  61 }