]> rtime.felk.cvut.cz Git - frescor/frsh.git/commitdiff
Updated FPGA terminology to math the deliverable
authorMichal Sojka <sojkam1@fel.cvut.cz>
Fri, 19 Dec 2008 14:33:31 +0000 (15:33 +0100)
committerMichal Sojka <sojkam1@fel.cvut.cz>
Fri, 19 Dec 2008 14:33:31 +0000 (15:33 +0100)
resources/fpga/Makefile.omk
resources/fpga/frm_fpga.c
resources/fpga/res_fpga.h
resources/fpga/res_fpga_idl.idl

index 2db2fa6497ad6cc6d1f6e088c1ace66a69df3dae..5c85569ffa7ac1edd8d565f97cfa41746621f846 100644 (file)
@@ -1,5 +1,5 @@
 default_CONFIG += CONFIG_RESOURCE_FPGA=y
-default_CONFIG += CONFIG_FPGA_COPROCESSORS=FRES_FPGA_CORRELATOR508_m
+default_CONFIG += CONFIG_FPGA_CORES=FRES_FPGA_CORRELATOR508_m
 
 ifeq ($(CONFIG_RESOURCE_FPGA),y)
 LOCAL_CONFIG_H = fpga_config.h
index 9279ce49ac524f834cdedafcba7556da2d85e2be..9ee33ca457f68b3513d57a9cac15b5914618693f 100644 (file)
@@ -13,7 +13,7 @@
  * State of the FPGA
  */
 struct fpga_state {
-       fres_coprocessors_t coprocessors; /**< Currently loaded coprocessors */
+       fres_cores_t cores; /**< Currently loaded cores */
 };
 
 int admission_test(struct fres_sa_scenario *scenario, void *priv, bool *schedulable)
@@ -26,8 +26,8 @@ int admission_test(struct fres_sa_scenario *scenario, void *priv, bool *schedula
 
                fpga = fres_contract_get_fpga(c->contract);
                if (fpga) {
-                       fres_coprocessors_t req = fpga->coprocessors;
-                       fres_coprocessors_t cur = data->coprocessors;
+                       fres_cores_t req = fpga->cores;
+                       fres_cores_t cur = data->cores;
                        if ((req & ~cur) != 0) *schedulable = false;
                        else *schedulable = true;
                } else {
@@ -41,7 +41,7 @@ int admission_test(struct fres_sa_scenario *scenario, void *priv, bool *schedula
 struct fpga_state fpga_state = {
        /* Currently only static FPGA configuration specified at
         * compile type is supported.  */
-       .coprocessors = CONFIG_FPGA_COPROCESSORS,
+       .cores = CONFIG_FPGA_CORES,
 };
 
 static const struct fres_res_manager frm = {
index 2beaab29c39671cf35ddc4f3fb3a597a50927d67..809e0464a4cd288b1e5c0bbece2b1e1ef9c76bf3 100644 (file)
@@ -16,7 +16,7 @@ FRES_CONTAINER_ACCESSOR(FPGA, fpga);
 /* Define fres_contract_(add|get|del)_fpga. */
 FRES_CONTRACT_ACCESSOR(fpga);
 
-/* Available FPGA coprocessors */
+/* Available FPGA cores */
 #define FRES_FPGA_TIMESTAMP_b          0
 #define FRES_FPGA_CORRELATOR508_b      1
 
index d1f56da25b999ec5f1acec8d183c3477e37086f5..22216e6d864d44bdaa02172b289ddcf151d89392 100644 (file)
@@ -6,10 +6,10 @@
  * @brief  Contract data block for FPGA resource
  */
 module fres {
-       typedef unsigned long long coprocessors_t;
+       typedef unsigned long long cores_t;
        module block {
                struct fpga {
-                       coprocessors_t coprocessors;
+                       cores_t cores;
                };
        };
 };