]> rtime.felk.cvut.cz Git - fpga/zynq/mzed-dc-control-hw.git/blob - motor_driver/MOTOR_DRIVER-cache.bck
Added folder cables containing files. These files describe how to make cables.
[fpga/zynq/mzed-dc-control-hw.git] / motor_driver / MOTOR_DRIVER-cache.bck
1 EESchema-DOCLIB  Version 2.0\r
2 #\r
3 $CMP 74LS86\r
4 D Quad XOR 2 inputs\r
5 K TTL XOR2\r
6 F 74xx/74ls86.pdf\r
7 $ENDCMP\r
8 #\r
9 #End Doc Library\r