]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/history - system/ip/canbench_cc_gpio
microzed_apo: Correct JX1_LVDS_21_N pin assignment on FPGA_IO header.
[fpga/zynq/canbench-sw.git] / system / ip / canbench_cc_gpio /
2016-05-12 Martin Jerabeksystem: added GPIO IP