]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-sw.git/history - system
scripts: include script for applying new FPGA design at runtime.
[fpga/zynq/canbench-sw.git] / system /
2016-05-24 Martin Jerabeksja1000: added module can_top for backward compatibility
2016-05-24 Martin Jerabekcan_crossbar: fixed STBY bit position in register
2016-05-17 Martin Jerabekxilinx_can: debugging, fixed timing problem, lowered...
2016-05-17 Martin Jerabekbootscript: changed IPs, updated paths
2016-05-16 Martin Jerabeksystem: removed reference to post-write_bitstream dist...
2016-05-16 Martin Jerabeksystem: updated build script for new Vivado version
2016-05-16 Martin Jerabekremoved outdated system.hdf
2016-05-16 Martin Jerabekupdated README, .gitignore
2016-05-16 Martin Jerabeksystem: added constraints file
2016-05-16 Martin Jerabeksystem: can_crossbar fixed and added to device tree...
2016-05-12 Martin Jerabekcan_crossbar: fixes (but still not working)
2016-05-12 Martin Jerabeksja1000: IP fixes, corrected device-tree entry, it...
2016-05-12 Martin Jerabeksystem: added GPIO IP
2016-05-12 Martin Jerabeksystem: added CAN crossbar IP
2016-05-12 Martin Jerabeksystem: updated scripts
2016-05-12 Martin Jerabeksja1000: synchronous with AXI, duplex register access...
2016-05-12 Martin Jerabeksja1000 core, linux drivers
2016-05-12 Martin Jerabekbitstream file renamed
2016-05-12 Martin Jerabekadded sja1000 IP
2016-04-01 Martin Jerabeksystem: build fix, removed generated HDL wrappers
2016-03-30 Martin Jerabekadded system and petalinux configuration, scripts,...