system/ip/sja1000_1.0/hdl/sja1000.v

   1 `include "timescale.v"
   2
   3         module sja1000 #
   4         (
   5                 // Users to add parameters here
   6
   7                 // User parameters ends
   8                 // Do not modify the parameters beyond this line
   9
  10
  11                 // Parameters of Axi Slave Bus Interface S00_AXI
  12                 parameter integer C_S00_AXI_DATA_WIDTH  = 32,
  13                 parameter integer C_S00_AXI_ADDR_WIDTH  = 8
  14
  15                 // Parameters of Axi Slave Bus Interface S_AXI_INTR
  16                 /*
  17                 parameter integer C_S_AXI_INTR_DATA_WIDTH       = 32,
  18                 parameter integer C_S_AXI_INTR_ADDR_WIDTH       = 5,
  19                 parameter integer C_NUM_OF_INTR = 1,
  20                 parameter  C_INTR_SENSITIVITY   = 32'hFFFFFFFF,
  21                 parameter  C_INTR_ACTIVE_STATE  = 32'hFFFFFFFF,
  22                 parameter integer C_IRQ_SENSITIVITY     = 1,
  23                 parameter integer C_IRQ_ACTIVE_STATE    = 1
  24                 */
  25         )
  26         (
  27                 // Users to add ports here
  28                 input  wire can_clk,
  29                 input  wire can_rx,
  30                 output wire can_tx,
  31                 output wire bus_off_on,
  32                 // User ports ends
  33                 // Do not modify the ports beyond this line
  34
  35
  36                 // Ports of Axi Slave Bus Interface S00_AXI
  37                 input wire  s00_axi_aclk,
  38                 input wire  s00_axi_aresetn,
  39                 input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_awaddr,
  40                 input wire [2 : 0] s00_axi_awprot,
  41                 input wire  s00_axi_awvalid,
  42                 output wire  s00_axi_awready,
  43                 input wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_wdata,
  44                 input wire [(C_S00_AXI_DATA_WIDTH/8)-1 : 0] s00_axi_wstrb,
  45                 input wire  s00_axi_wvalid,
  46                 output wire  s00_axi_wready,
  47                 output wire [1 : 0] s00_axi_bresp,
  48                 output wire  s00_axi_bvalid,
  49                 input wire  s00_axi_bready,
  50                 input wire [C_S00_AXI_ADDR_WIDTH-1 : 0] s00_axi_araddr,
  51                 input wire [2 : 0] s00_axi_arprot,
  52                 input wire  s00_axi_arvalid,
  53                 output wire  s00_axi_arready,
  54                 output wire [C_S00_AXI_DATA_WIDTH-1 : 0] s00_axi_rdata,
  55                 output wire [1 : 0] s00_axi_rresp,
  56                 output wire  s00_axi_rvalid,
  57                 input wire  s00_axi_rready,
  58
  59                 // Ports of Axi Slave Bus Interface S_AXI_INTR
  60                 /*
  61                 input wire  s_axi_intr_aclk,
  62                 input wire  s_axi_intr_aresetn,
  63                 input wire [C_S_AXI_INTR_ADDR_WIDTH-1 : 0] s_axi_intr_awaddr,
  64                 input wire [2 : 0] s_axi_intr_awprot,
  65                 input wire  s_axi_intr_awvalid,
  66                 output wire  s_axi_intr_awready,
  67                 input wire [C_S_AXI_INTR_DATA_WIDTH-1 : 0] s_axi_intr_wdata,
  68                 input wire [(C_S_AXI_INTR_DATA_WIDTH/8)-1 : 0] s_axi_intr_wstrb,
  69                 input wire  s_axi_intr_wvalid,
  70                 output wire  s_axi_intr_wready,
  71                 output wire [1 : 0] s_axi_intr_bresp,
  72                 output wire  s_axi_intr_bvalid,
  73                 input wire  s_axi_intr_bready,
  74                 input wire [C_S_AXI_INTR_ADDR_WIDTH-1 : 0] s_axi_intr_araddr,
  75                 input wire [2 : 0] s_axi_intr_arprot,
  76                 input wire  s_axi_intr_arvalid,
  77                 output wire  s_axi_intr_arready,
  78                 output wire [C_S_AXI_INTR_DATA_WIDTH-1 : 0] s_axi_intr_rdata,
  79                 output wire [1 : 0] s_axi_intr_rresp,
  80                 output wire  s_axi_intr_rvalid,
  81                 input wire  s_axi_intr_rready,
  82                 */
  83                 output wire  irq
  84         );
  85         wire reg_we;
  86         wire reg_cs;
  87         wire reg_rst;
  88         wire [7:0] reg_data_in;
  89         wire [7:0] reg_data_out;
  90         wire [7:0] reg_addr;
  91
  92         wire irq_n;
  93         assign irq = ~irq_n;
  94
  95 // Instantiation of Axi Bus Interface S00_AXI
  96         can_ifc_axi # (
  97                 .C_S_AXI_DATA_WIDTH(C_S00_AXI_DATA_WIDTH),
  98                 .C_S_AXI_ADDR_WIDTH(C_S00_AXI_ADDR_WIDTH)
  99         ) can_ifc_axi_inst (
 100                 .S_AXI_ACLK(s00_axi_aclk),
 101                 .S_AXI_ARESETN(s00_axi_aresetn),
 102                 .S_AXI_AWADDR(s00_axi_awaddr),
 103                 .S_AXI_AWPROT(s00_axi_awprot),
 104                 .S_AXI_AWVALID(s00_axi_awvalid),
 105                 .S_AXI_AWREADY(s00_axi_awready),
 106                 .S_AXI_WDATA(s00_axi_wdata),
 107                 .S_AXI_WSTRB(s00_axi_wstrb),
 108                 .S_AXI_WVALID(s00_axi_wvalid),
 109                 .S_AXI_WREADY(s00_axi_wready),
 110                 .S_AXI_BRESP(s00_axi_bresp),
 111                 .S_AXI_BVALID(s00_axi_bvalid),
 112                 .S_AXI_BREADY(s00_axi_bready),
 113                 .S_AXI_ARADDR(s00_axi_araddr),
 114                 .S_AXI_ARPROT(s00_axi_arprot),
 115                 .S_AXI_ARVALID(s00_axi_arvalid),
 116                 .S_AXI_ARREADY(s00_axi_arready),
 117                 .S_AXI_RDATA(s00_axi_rdata),
 118                 .S_AXI_RRESP(s00_axi_rresp),
 119                 .S_AXI_RVALID(s00_axi_rvalid),
 120                 .S_AXI_RREADY(s00_axi_rready),
 121
 122                 .clk_i(can_clk),
 123                 .reg_rst_o(reg_rst),
 124                 .reg_cs_o(reg_cs),
 125                 .reg_we_o(reg_we),
 126                 .reg_addr_o(reg_addr),
 127                 .reg_data_in_o(reg_data_in),
 128                 .reg_data_out_i(reg_data_out)
 129         );
 130
 131         can_top_raw can_top_raw_inst (
 132                 .reg_we_i(reg_we),
 133                 .reg_cs_i(reg_cs),
 134                 .reg_data_in(reg_data_in),
 135                 .reg_data_out(reg_data_out),
 136                 .reg_addr_i(reg_addr),
 137                 .reg_rst_i(reg_rst),
 138
 139                 .clk_i(can_clk),
 140                 .rx_i(can_rx),
 141                 .tx_o(can_tx),
 142                 .bus_off_on(bus_off_on),
 143                 .irq_on(irq_n),
 144                 .clkout_o()
 145         );
 146
 147 // Instantiation of Axi Bus Interface S_AXI_INTR
 148 /*
 149         SJA1000_v1_0_S_AXI_INTR # (
 150                 .C_S_AXI_DATA_WIDTH(C_S_AXI_INTR_DATA_WIDTH),
 151                 .C_S_AXI_ADDR_WIDTH(C_S_AXI_INTR_ADDR_WIDTH),
 152                 .C_NUM_OF_INTR(C_NUM_OF_INTR),
 153                 .C_INTR_SENSITIVITY(C_INTR_SENSITIVITY),
 154                 .C_INTR_ACTIVE_STATE(C_INTR_ACTIVE_STATE),
 155                 .C_IRQ_SENSITIVITY(C_IRQ_SENSITIVITY),
 156                 .C_IRQ_ACTIVE_STATE(C_IRQ_ACTIVE_STATE)
 157         ) SJA1000_v1_0_S_AXI_INTR_inst (
 158                 .S_AXI_ACLK(s_axi_intr_aclk),
 159                 .S_AXI_ARESETN(s_axi_intr_aresetn),
 160                 .S_AXI_AWADDR(s_axi_intr_awaddr),
 161                 .S_AXI_AWPROT(s_axi_intr_awprot),
 162                 .S_AXI_AWVALID(s_axi_intr_awvalid),
 163                 .S_AXI_AWREADY(s_axi_intr_awready),
 164                 .S_AXI_WDATA(s_axi_intr_wdata),
 165                 .S_AXI_WSTRB(s_axi_intr_wstrb),
 166                 .S_AXI_WVALID(s_axi_intr_wvalid),
 167                 .S_AXI_WREADY(s_axi_intr_wready),
 168                 .S_AXI_BRESP(s_axi_intr_bresp),
 169                 .S_AXI_BVALID(s_axi_intr_bvalid),
 170                 .S_AXI_BREADY(s_axi_intr_bready),
 171                 .S_AXI_ARADDR(s_axi_intr_araddr),
 172                 .S_AXI_ARPROT(s_axi_intr_arprot),
 173                 .S_AXI_ARVALID(s_axi_intr_arvalid),
 174                 .S_AXI_ARREADY(s_axi_intr_arready),
 175                 .S_AXI_RDATA(s_axi_intr_rdata),
 176                 .S_AXI_RRESP(s_axi_intr_rresp),
 177                 .S_AXI_RVALID(s_axi_intr_rvalid),
 178                 .S_AXI_RREADY(s_axi_intr_rready),
 179                 .irq(irq)
 180         );*/
 181
 182         // Add user logic here
 183
 184         // User logic ends
 185
 186         endmodule