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rtime.felk.cvut.cz Git - fpga/zynq/canbench-hw.git/log
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Martin Jerabek [Tue, 15 Mar 2016 12:40:11 +0000 (13:40 +0100)]
Separated to hierarchical sheets.
Martin Jerabek [Tue, 15 Mar 2016 12:08:15 +0000 (13:08 +0100)]
vcco renamed to vccio
Martin Jerabek [Tue, 15 Mar 2016 12:01:44 +0000 (13:01 +0100)]
Added 2nd microheader.
Martin Jerabek [Mon, 14 Mar 2016 19:55:54 +0000 (20:55 +0100)]
Added basic schema with 4x CAN Transceiver and 1x MicroHeader.
Pavel Pisa [Fri, 4 Mar 2016 09:54:39 +0000 (10:54 +0100)]
Initialize KiCad design of 4 channel CAN transceiver board for MicroZed board
Signed-off-by: Pavel Pisa <pisa@cmp.felk.cvut.cz>
projects / fpga / zynq / canbench-hw.git / log