]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-hw.git/commit
layout: fixes, silk screen
authorMartin Jerabek <jerabma7@fel.cvut.cz>
Fri, 22 Apr 2016 01:44:23 +0000 (03:44 +0200)
committerMartin Jerabek <jerabma7@fel.cvut.cz>
Fri, 22 Apr 2016 01:44:23 +0000 (03:44 +0200)
commit704527dbdf2f971bb512dbbe77b0a7754b434902
tree75c68a425bd95530f3ec0441677608ae6c174bd9
parentc7e72401970d4b590c8012d96ddd67e84039fb31
layout: fixes, silk screen
13 files changed:
canbench-hw.kicad_pcb
output/canbench-hw-B.Cu.gbr [new file with mode: 0644]
output/canbench-hw-B.Mask.gbr [new file with mode: 0644]
output/canbench-hw-B.SilkS.gbr [new file with mode: 0644]
output/canbench-hw-Edge.Cuts.gbr [new file with mode: 0644]
output/canbench-hw-F.Cu.gbr [new file with mode: 0644]
output/canbench-hw-F.Mask.gbr [new file with mode: 0644]
output/canbench-hw-F.SilkS.gbr [new file with mode: 0644]
output/canbench-hw-NPTH-drl_map.gbr [new file with mode: 0644]
output/canbench-hw-NPTH.drl [new file with mode: 0644]
output/canbench-hw-drl.rpt [new file with mode: 0644]
output/canbench-hw-drl_map.gbr [new file with mode: 0644]
output/canbench-hw.drl [new file with mode: 0644]