layout: fixes, silk screen

[fpga/zynq/canbench-hw.git] / output / canbench-hw-drl.rpt

diff --git a/output/canbench-hw-drl.rpt b/output/canbench-hw-drl.rpt
new file mode 100644 (file)
index 0000000..7c6f52b
--- /dev/null
+++ b/output/canbench-hw-drl.rpt
@@ -0,0 +1,31 @@
+Drill report for /home/martin/projects/cvut/bakalarka/canbench-hw/canbench-hw.kicad_pcb
+Created on Pá 22. duben 2016, 03:40:49 CEST
+
+Copper Layer Stackup:
+    =============================================================
+    L1 :  F.Cu                      front
+    L2 :  B.Cu                      back
+
+
+Drill file 'canbench-hw.drl' contains
+    plated through holes:
+    =============================================================
+    T1  0,40mm  0,016"  (227 holes)
+    T2  0,64mm  0,025"  (5 holes)
+    T3  0,76mm  0,030"  (16 holes)
+    T4  0,82mm  0,032"  (2 holes)
+    T5  1,00mm  0,039"  (3 holes)  (with 3 slots)
+    T6  1,02mm  0,040"  (150 holes)
+    T7  1,23mm  0,048"  (2 holes)
+    T8  3,05mm  0,120"  (8 holes)
+    T9  3,20mm  0,126"  (8 holes)
+
+    Total plated holes count 421
+
+
+Drill file 'canbench-hw-NPTH.drl' contains
+    unplated through holes:
+    =============================================================
+    T1  2,30mm  0,091"  (1 hole)
+
+    Total unplated holes count 1