added initial PCB layout

[fpga/zynq/canbench-hw.git] / canbench-hw.sch

diff --git a/canbench-hw.sch b/canbench-hw.sch
index 1327ee5923f35a52896858a3e8abd050828cceea..9824d2960bfc32d5713e53e3734ee959c4f72c9d 100644 (file)
--- a/canbench-hw.sch
+++ b/canbench-hw.sch
@@ -71,12 +71,12 @@ LIBS:ttl_ieee
 LIBS:video
 LIBS:Xicor
 LIBS:Zilog
-LIBS:conn_100pin
 LIBS:MCP2562FD
 LIBS:vccio
 LIBS:mcp
 LIBS:JX1
 LIBS:JX2
+LIBS:gates
 LIBS:canbench-hw-cache
 EELAYER 25 0
 EELAYER END
@@ -117,7 +117,7 @@ L C C1
 U 1 1 56E96856
 P 1550 5100
 F 0 "C1" H 1575 5200 50  0000 L CNN
-F 1 "100nF" H 1575 5000 50  0000 L CNN
+F 1 "10n" H 1575 5000 50  0000 L CNN
 F 2 "Capacitors_SMD:C_0805_HandSoldering" H 1588 4950 50  0001 C CNN
 F 3 "" H 1550 5100 50  0000 C CNN
        1    1550 5100
@@ -266,10 +266,10 @@ Wire Wire Line
 Text Label 7400 1250 0    60   ~ 0
 PWR_ENABLE
 $Comp
-L SW_PUSH SW7
+L SW_PUSH SW2
 U 1 1 57114B25
 P 1150 6050
-F 0 "SW7" H 1300 6160 50  0000 C CNN
+F 0 "SW2" H 1300 6160 50  0000 C CNN
 F 1 "SW_PUSH" H 1150 5970 50  0000 C CNN
 F 2 "Buttons_Switches_SMD:SW_SPST_EVQP0" H 1150 6050 50  0001 C CNN
 F 3 "" H 1150 6050 50  0000 C CNN
@@ -277,11 +277,11 @@ F 3 "" H 1150 6050 50  0000 C CNN
        1    0    0    -1  
 $EndComp
 $Comp
-L C C43
+L C C2
 U 1 1 57114B2C
 P 1550 6300
-F 0 "C43" H 1575 6400 50  0000 L CNN
-F 1 "100nF" H 1575 6200 50  0000 L CNN
+F 0 "C2" H 1575 6400 50  0000 L CNN
+F 1 "10n" H 1575 6200 50  0000 L CNN
 F 2 "Capacitors_SMD:C_0805_HandSoldering" H 1588 6150 50  0001 C CNN
 F 3 "" H 1550 6300 50  0000 C CNN
        1    1550 6300