]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-hw.git/blob - lib/gates.dcm
footprints positioned, better D-SUB footprints, fixes
[fpga/zynq/canbench-hw.git] / lib / gates.dcm
1 EESchema-DOCLIB  Version 2.0
2 #
3 $CMP 74HCT245
4 D Octal bus transceiver, 3-state
5 K 3-state octal bus transceiver
6 F http://www.tme.eu/en/Document/6b9c9e3c1f2cabc2004604fd7fafbc4d/74HC_HCT245.pdf
7 $ENDCMP
8 #
9 $CMP 74HCT86D
10 D Quad 2-input XOR gate
11 K Quad XOR2
12 F http://www.tme.eu/cz/Document/e5c7873dd02a97037a31fef9672a6b99/74HCT86D.652.pdf
13 $ENDCMP
14 #
15 #End Doc Library