]> rtime.felk.cvut.cz Git - fpga/zynq/canbench-hw.git/blob - lib/JX1.dcm
power reg changed, I/O pin assignment, testpoints, CAN
[fpga/zynq/canbench-hw.git] / lib / JX1.dcm
1 EESchema-DOCLIB  Version 2.0
2 #
3 $CMP MicroZed_JX1
4 D Bergstak 61083-10
5 $ENDCMP
6 #
7 #End Doc Library