Correct baud-rate set.

[fpga/virtex2/plasma.git] / top_plasma.vhd

diff --git a/top_plasma.vhd b/top_plasma.vhd
index 17dee5cca291a7ada84aff9d8f6be5954fb951ce..e1afb635a295ce64388e4e102467a64b61ac89dc 100644 (file)
--- a/top_plasma.vhd
+++ b/top_plasma.vhd
@@ -25,12 +25,13 @@ begin
   reset <= not RESET_N;
   
   
-  plasma_1: entity work.plasma
+  plasma_1 : entity work.plasma
     generic map (
-      memory_type => "XILINX_16X",
-      log_file    => "UNUSED",
-      ethernet    => '0',
-      use_cache   => '0')
+      memory_type    => "XILINX_16X",
+      log_file       => "UNUSED",
+      ethernet       => '0',
+      use_cache      => '0',
+      uart_prescaler => 207)            -- 115200 baud
     port map (
       clk          => clk,
       reset        => reset,