Modified sine wave output.

[fpga/virtex2/msp_motion.git] / msp_motion.vhd

diff --git a/msp_motion.vhd b/msp_motion.vhd
index 2d2f3f496a1ca2ff11644cb8252c38bb6d49a748..a9769487189263d0f25fa4623bde65272e8d8dab 100644 (file)
--- a/msp_motion.vhd
+++ b/msp_motion.vhd
@@ -41,6 +41,8 @@ end msp_motion;
 
 architecture rtl of msp_motion is
 
+  signal reset_p : std_logic;
+
   ------------------------------------------------------------------------------
   -- OpenMSP430 softcore MCU module
   ------------------------------------------------------------------------------
@@ -60,6 +62,7 @@ architecture rtl of msp_motion is
   signal per_en    : std_logic;
   signal per_addr  : std_logic_vector (7 downto 0);
   -- Interrupt
+  --signal irq       : std_logic_vector (13 downto 0) := (others => '0');
   signal irq       : std_logic_vector (13 downto 0);
   signal irq_acc   : std_logic_vector (13 downto 0);
 
@@ -87,7 +90,7 @@ architecture rtl of msp_motion is
   signal DPA_SEL     : std_logic;
   signal DPA_STB     : std_logic;
   -- Auxiliary register used to generate IRF_ACK
-  signal IRF_ACK_REG : std_logic;
+  signal IRF_ACK_REG : std_logic := '0';
   -- Auxiliary signal used to form B-port address
   signal DPB_ADR     : std_logic_vector (9 downto 0);
 
@@ -142,7 +145,7 @@ begin
     port map (
       dco_clk                  => CLK_24MHz,
       lfxt_clk                 => '0',
-      reset_n                  => RESET,
+      reset_n                  => '1',
       rxd                      => RXD,
       txd                      => TXD,
       per_addr                 => per_addr,
@@ -156,13 +159,24 @@ begin
       aclk_en                  => open,
       smclk_en                 => open,
       mclk                     => mclk,
-      puc                      => puc,
+      puc                      => open,
       dmem_addr                => dmem_addr,
       dmem_ce                  => dmem_ce,
       dmem_we                  => dmem_we,
       dmem_din                 => dmem_din,
       dmem_dout                => dmem_dout);
 
+  puc     <= '0';
+  reset_p <= not RESET;
+
+  STARTUP_VIRTEX2_inst : STARTUP_VIRTEX2
+    port map (
+      CLK => open,
+      -- Clock input for start-up sequence
+      GSR => reset_p, -- Global Set/Reset input (GSR cannot be used for the port name)
+      GTS => open); -- Global 3-state input (GTS cannot be used for the port name)
+
+
   -- External data bus address decoder and data multiplexer.
   ------------------------------------------------------------------------------
   -- When connection more memories, be aware that 'dmem_dout' can vary only when
@@ -403,12 +417,13 @@ begin
       pwm     => PWM3_OUT);
 
   -- PWM signals mapped to FPGA outputs, EN forced to '1'
-  PWM0    <= PWM1_OUT;
+  PWM0    <= not PWM1_OUT;
   PWM0_EN <= '1';
-  PWM1    <= PWM2_OUT;
+  PWM1    <= not PWM2_OUT;
   PWM1_EN <= '1';
-  PWM2    <= PWM3_OUT;
+  PWM2    <= not PWM3_OUT;
   PWM2_EN <= '1';
+
   -- PWM is signalized on LEDs
   LED0    <= PWM1_OUT;
   LED1    <= PWM2_OUT;