Modified sine wave output.

[fpga/virtex2/msp_motion.git] / msp_motion.vhd

diff --git a/msp_motion.vhd b/msp_motion.vhd
index 2e949871860b00ac85c56a9af05dc877d2527506..a9769487189263d0f25fa4623bde65272e8d8dab 100644 (file)
--- a/msp_motion.vhd
+++ b/msp_motion.vhd
@@ -62,6 +62,7 @@ architecture rtl of msp_motion is
   signal per_en    : std_logic;
   signal per_addr  : std_logic_vector (7 downto 0);
   -- Interrupt
+  --signal irq       : std_logic_vector (13 downto 0) := (others => '0');
   signal irq       : std_logic_vector (13 downto 0);
   signal irq_acc   : std_logic_vector (13 downto 0);
 
@@ -89,7 +90,7 @@ architecture rtl of msp_motion is
   signal DPA_SEL     : std_logic;
   signal DPA_STB     : std_logic;
   -- Auxiliary register used to generate IRF_ACK
-  signal IRF_ACK_REG : std_logic;
+  signal IRF_ACK_REG : std_logic := '0';
   -- Auxiliary signal used to form B-port address
   signal DPB_ADR     : std_logic_vector (9 downto 0);
 
@@ -416,12 +417,13 @@ begin
       pwm     => PWM3_OUT);
 
   -- PWM signals mapped to FPGA outputs, EN forced to '1'
-  PWM0    <= PWM1_OUT;
+  PWM0    <= not PWM1_OUT;
   PWM0_EN <= '1';
-  PWM1    <= PWM2_OUT;
+  PWM1    <= not PWM2_OUT;
   PWM1_EN <= '1';
-  PWM2    <= PWM3_OUT;
+  PWM2    <= not PWM3_OUT;
   PWM2_EN <= '1';
+
   -- PWM is signalized on LEDs
   LED0    <= PWM1_OUT;
   LED1    <= PWM2_OUT;